公开(公告)号：US08030661B2

公开(公告)日：2011-10-04

申请号：US12439451

申请日：2007-08-22

Applicant: Morimitsu Sekimoto ,  Hitoshi Haga ,  Kenichi Sakakibara ,  Reiji Kawashima ,  Abdallah Mechi ,  Toshiyuki Maeda

Inventor： Morimitsu Sekimoto ,  Hitoshi Haga ,  Kenichi Sakakibara ,  Reiji Kawashima ,  Abdallah Mechi ,  Toshiyuki Maeda

IPC: H01L31/0312 ,  H01L23/52 ,  H01L23/34

CPC classification number: H01L25/16 ,  H01L23/647 ,  H01L24/48 ,  H01L25/072 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/4899 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3011 ,  H05K1/0201 ,  H05K1/0204 ,  H05K1/141 ,  H05K1/18 ,  H05K2201/062 ,  H05K2201/09263 ,  H05K2201/09972 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2203/081 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: In the case where a chip is made of wide band gap semiconductor, a power conversion apparatus is obtained in which a component having a low heat resistant temperature is prevented from receiving thermal damage by heat generated at the chip. In a configuration including: a chip portion (20) including a chip (21) made of wide band gap semiconductor and a member (22, 23) having a heat resistant temperature equal to or higher than that of the chip (21); and a peripheral component (25) arranged in the vicinity of the chip portion (20) and having a heat resistant temperature lower than that of the chip (21). The chip (21) and the peripheral component (25) are thermally insulated from each other so that the temperature of the peripheral component (25) does not exceed the heat resistant temperature of the peripheral component (25).

Abstract translation: 在芯片由宽带隙半导体制成的情况下，可以获得能够防止耐热温度低的部件受到芯片产生的热量的热损伤的电力转换装置。 一种构造，包括：包括由宽带隙半导体制成的芯片（21）的芯片部分（20）和具有等于或高于芯片（21）的耐热温度的部件（22,23）; 以及布置在所述芯片部分（20）附近并且具有比所述芯片（21）的耐热温度低的耐热温度的外围部件（25）。 芯片（21）和周边部件（25）彼此绝热，使得周边部件（25）的温度不超过外围部件（25）的耐热温度。

公开(公告)号：US20110037755A1

公开(公告)日：2011-02-17

申请号：US12988582

申请日：2010-04-02

Applicant: Toshiyuki Maeda ,  Yutaka Yoshihama ,  Shinya Tsuchida

Inventor： Toshiyuki Maeda ,  Yutaka Yoshihama ,  Shinya Tsuchida

IPC: G09G5/00 ,  G09G3/28

CPC classification number: G09G3/293 ,  G09G3/2927 ,  G09G2310/0218 ,  G09G2310/0267

Abstract: A driving method of an alternating-current surface discharge type PDP is provided. In the initializing period. an operation that applies a predetermined voltage for causing discharge regardless of the presence or absence of the former discharge to a scan electrode and causes the initializing discharge in the discharge cell is assumed as a forcibly initializing operation. In the address period, the time when a scan pulse is applied to the scan electrode and an address pulse is applied to the data electrode is assumed to be address time. In each of discharge cells, the forcibly initializing operation is performed in one of a plurality of fields, and the address time in the address period of a field that does not, undergo the forcibly initializing operation is set to be longer than the address time in the address period of a field that undergoes the forcibly initializing operation.

Abstract translation: 提供了一种交流表面放电型PDP的驱动方法。 在初始化期间。 无论是否存在对扫描电极的存在或不存在，并且使放电单元中的初始化放电被假设为强制初始化操作，则施加用于引起放电的预定电压的操作。 在寻址周期中，将扫描脉冲施加到扫描电极的时间和地址脉冲施加到数据电极被认为是寻址时间。 在每个放电单元中，强制初始化操作在多个场中的一个场中执行，并且未经过强制初始化操作的场的地址周期中的地址时间被设置为长于地址时间 经过强制初始化操作的字段的寻址周期。

公开(公告)号：US20100309700A1

公开(公告)日：2010-12-09

申请号：US12865590

申请日：2009-01-21

Applicant: Toshiyuki Maeda ,  Morimitsu Sekimoto ,  Hiroshi Hibino

Inventor： Toshiyuki Maeda ,  Morimitsu Sekimoto ,  Hiroshi Hibino

IPC: H02M7/06

CPC classification number: H02M7/797 ,  H02M7/5387 ,  H02M2001/0051 ,  H02M2007/2195 ,  H03K17/08142 ,  Y02B70/1408 ,  Y02B70/1483 ,  Y02B70/1491

Abstract: An inverter circuit (120) is configured so as to perform synchronous rectification by six switching elements (130). The switching element (130) is formed of an unipolar device (SiC MOSFET in this case) using a wideband gap semiconductor. The inverter circuit (120) uses the body diode (131) of SiC MOSFET (130) as a freewheeling diode during synchronous rectification.

Abstract translation: 逆变器电路（120）被构造成通过六个开关元件（130）进行同步整流。 开关元件（130）由使用宽带隙半导体的单极器件（在这种情况下为SiC MOSFET）形成。 逆变器电路（120）在同步整流期间使用SiC MOSFET（130）的体二极管（131）作为续流二极管。

公开(公告)号：US20100118056A1

公开(公告)日：2010-05-13

申请号：US11995021

申请日：2007-07-06

Applicant: Takahiko Origuchi ,  Hidehiko Shoji ,  Mitsuo Ueda ,  Toshiyuki Maeda

Inventor： Takahiko Origuchi ,  Hidehiko Shoji ,  Mitsuo Ueda ,  Toshiyuki Maeda

IPC: G09G5/10

CPC classification number: G09G3/2965 ,  G09G3/2022 ,  G09G3/294 ,  G09G2310/066

Abstract: In a plasma display device and a method for driving a plasma display panel, fluctuation of emission luminance of a discharge cell is reduced and display quality of an image is improved. The plasma display device is provided with a plasma display panel having a plurality of scanning electrodes and sustaining electrodes which configure a display electrode pair. The plasma display device is also provided with a sustaining pulse generating circuit, which has a plurality of subfields having an initializing period, a writing period and a sustaining period in one field period, and generates three kinds of sustaining pulses, i.e., a first sustaining pulse to be reference, a second sustaining pulse whose start-up is sharper than that of the first sustaining pulse and that of a third sustaining pulse, and the third sustaining pulse whose trailing edge is sharper than that of the first sustaining pulse and that of the second sustaining pulse, by periodically switching the pulses. In a sustaining period of at least one subfield in one field period, the third sustaining pulse is applied to one electrode of the electrode pair, then just after the application, the second sustaining pulse is applied to the other electrode of the display electrode pair.

Abstract translation: 在等离子体显示装置和等离子体显示面板的驱动方法中，放电单元的发光亮度的变动减小，图像的显示品质提高。 等离子体显示装置设置有具有构成显示电极对的多个扫描电极和维持电极的等离子体显示面板。 等离子体显示装置还具有维持脉冲发生电路，其具有在一个场周期中具有初始化周期，写入周期和维持周期的多个子场，并且产生三种维持脉冲，即，第一维持 脉冲作为参考，第二维持脉冲的启动比第一维持脉冲和第三维持脉冲的启动更尖锐，第三维持脉冲的后沿比第一维持脉冲更尖锐， 第二维持脉冲，通过周期性地切换脉冲。 在一个场周期中的至少一个子场的维持周期中，将第三维持脉冲施加到电极对的一个电极，然后在施加之后，将第二维持脉冲施加到显示电极对的另一个电极。

公开(公告)号：US20090256161A1

公开(公告)日：2009-10-15

申请号：US12439451

申请日：2007-08-22

Applicant: Morimitsu Sekimoto ,  Hitoshi Haga ,  Kenichi Sakakibara ,  Reiji Kawashima ,  Abdallah Mechi ,  Toshiyuki Maeda

Inventor： Morimitsu Sekimoto ,  Hitoshi Haga ,  Kenichi Sakakibara ,  Reiji Kawashima ,  Abdallah Mechi ,  Toshiyuki Maeda

IPC: H01L29/24 ,  H01L23/34

CPC classification number: H01L25/16 ,  H01L23/647 ,  H01L24/48 ,  H01L25/072 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/4899 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3011 ,  H05K1/0201 ,  H05K1/0204 ,  H05K1/141 ,  H05K1/18 ,  H05K2201/062 ,  H05K2201/09263 ,  H05K2201/09972 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2203/081 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: In the case where a chip is made of wide band gap semiconductor, a power conversion apparatus is obtained in which a component having a low heat resistant temperature is prevented from receiving thermal damage by heat generated at the chip. In a configuration including: a chip portion (20) including a chip (21) made of wide band gap semiconductor and a member (22, 23) having a heat resistant temperature equal to or higher than that of the chip (21); and a peripheral component (25) arranged in the vicinity of the chip portion (20) and having a heat resistant temperature lower than that of the chip (21). The chip (21) and the peripheral component (25) are thermally insulated from each other so that the temperature of the peripheral component (25) does not exceed the heat resistant temperature of the peripheral component (25).

Abstract translation: 在芯片由宽带隙半导体制成的情况下，可以获得能够防止耐热温度低的部件受到芯片产生的热量的热损伤的电力转换装置。 一种构造，包括：包括由宽带隙半导体制成的芯片（21）的芯片部分（20）和具有等于或高于芯片（21）的耐热温度的部件（22,23）; 以及布置在所述芯片部分（20）附近并且具有比所述芯片（21）的耐热温度低的耐热温度的外围部件（25）。 芯片（21）和周边部件（25）彼此绝热，使得周边部件（25）的温度不超过外围部件（25）的耐热温度。

公开(公告)号：US20090237330A1

公开(公告)日：2009-09-24

申请号：US12092102

申请日：2007-08-09

Applicant: Hidehiko Shoji ,  Takahiko Origuchi ,  Toshiyuki Maeda ,  Mitsuo Ueda ,  Takayuki Kamatani

Inventor： Hidehiko Shoji ,  Takahiko Origuchi ,  Toshiyuki Maeda ,  Mitsuo Ueda ,  Takayuki Kamatani

IPC: G09G3/28

CPC classification number: G09G3/2803 ,  G09G3/2022 ,  G09G3/2096 ,  G09G3/2932 ,  G09G3/2942 ,  G09G3/2948 ,  G09G3/2965

Abstract: In a plasma display device, a period for connecting display electrode pairs to the base potential is disposed between a sustain pulse for generating the final sustain discharge and the previous sustain pulse based on a lighting ratio of the discharge cells in the corresponding subfield, and a voltage for reducing an interelectrode potential difference of the display electrode pairs is applied to the display electrode pairs in a predetermined time period corresponding to the lighting ratio of the discharge cells in the corresponding subfield after applying the sustain pulse for generating the final sustain discharge to the scan electrodes.

Abstract translation: 在等离子体显示装置中，将用于将显示电极对与基极电位连接的期间设置在用于产生最终维持放电的维持脉冲和基于相应子场中的放电单元的点亮率的先前维持脉冲之间， 在将用于产生最终维持放电的维持脉冲施加到相应子场中的放电单元的点亮比例的预定时间段内，将显示电极对的电极间电位差降低的电压施加到显示电极对 扫描电极。

公开(公告)号：US20090052116A1

公开(公告)日：2009-02-26

申请号：US11909576

申请日：2006-03-24

Applicant: Toshiyuki Maeda ,  Masanori Goudo ,  Katsutoshi Sugi ,  Hideshige Nakagawa ,  Satoshi Kubota

Inventor： Toshiyuki Maeda ,  Masanori Goudo ,  Katsutoshi Sugi ,  Hideshige Nakagawa ,  Satoshi Kubota

IPC: H01G9/155

CPC classification number: H01G9/016 ,  H01G2/06 ,  H01G9/155 ,  H01G11/12 ,  H01G11/82 ,  Y02E60/13

Abstract: A plurality of capacitor cells (10) are layered to form a cell group. On the top of each capacitor cell (10), a pair of electrode plates (10b) is formed to protrude upward. The adjacent electrode plates (10b) are connected to each other. A connection piece (20) protruding upward is attached to each of the electrode plates (10b). The connection piece (20) is connected to a circuit substrate (30). Thus, it is possible to effectively make a connection between the cell group of the capacitor cells (10) and the circuit substrate (30).

Abstract translation: 层叠多个电容器单元（10）以形成单元组。 在每个电容器单元（10）的顶部，形成一对电极板（10b）向上突出。 相邻的电极板（10b）彼此连接。 向上突出的连接片（20）附接到每个电极板（10b）。 连接件（20）连接到电路基板（30）。 因此，可以有效地形成电容器单元（10）的单元组与电路基板（30）之间的连接。

公开(公告)号：US20070299181A1

公开(公告)日：2007-12-27

申请号：US11607060

申请日：2006-12-01

Applicant: Kazuyuki Nakata ,  Norihiko Sato ,  Toshiyuki Maeda ,  David Walsh ,  Herbert Bendler

Inventor： Kazuyuki Nakata ,  Norihiko Sato ,  Toshiyuki Maeda ,  David Walsh ,  Herbert Bendler

IPC: C08L23/00

CPC classification number: C08L23/0846 ,  C08L23/0853 ,  C08L23/14 ,  C08L2205/02 ,  C08L2666/06

Abstract: A partially cross-linked polymer composition obtainable by dynamically heat-treating: 95 to 50% by weight of a resin (A) comprising a defined ethylene copolymer, and 5 to 50% by weight of a resin (B) comprising a two or more-component propylene copolymer containing 0.1 to 20% by mol of units derived from α-olefins other than propylene, or a blend of the two or more-component propylene copolymer and a propylene homopolymer which can be in the presence of defined amount of an organic peroxide (C) based on 100 parts by weight of the total amount of the resins (A) and (B). A process for producing the polymer compositions is also provided.

Abstract translation: 通过动态热处理可获得的部分交联的聚合物组合物：95至50重量％的包含限定的乙烯共聚物的树脂（A）和5至50重量％的包含两个或更多个 - 含有0.1-20摩尔％的来自除丙烯以外的α-烯烃的单元的组分丙烯共聚物，或两种或更多种成分丙烯共聚物和丙烯均聚物的共混物，其可以在规定量的有机物存在下 基于树脂（A）和（B）的总量100重量份的过氧化物（C）。 还提供了制备聚合物组合物的方法。

公开(公告)号：US07180263B2

公开(公告)日：2007-02-20

申请号：US10416271

申请日：2001-11-09

Applicant: Toshiyuki Maeda ,  Manabu Kosaka ,  Masanobu Kita

Inventor： Toshiyuki Maeda ,  Manabu Kosaka ,  Masanobu Kita

IPC: H02P6/00 ,  H02K7/00

CPC classification number: H02P6/10 ,  H02P6/085 ,  H02P6/28 ,  H02P25/089

Abstract: Synchronous motor controlling apparatus and method controls power applied to minimize or eliminate speed variations of a synchronous motor due to variations in load imposed the motor. The rotational position of a rotor of the synchronous motor based on the input terminal voltages and currents to the synchronous motor, and the power applied to the motor is adjusted accordingly. Higher harmonics of the input voltages and currents may also be used to detect the position of the rotor. In addition, the apparatus and method also accounts for the varying speed command inputs.

Abstract translation: 同步电动机控制装置和方法控制由于施加电动机的负载变化而使同步电动机的速度变化最小化或消除的功率。 基于向同步电动机的输入端子电压和电流的同步电动机的转子的旋转位置以及施加到电动机的功率进行相应调整。 输入电压和电流的高次谐波也可用于检测转子的位置。 此外，该装置和方法还考虑了变速命令输入。

公开(公告)号：US20050182587A1

公开(公告)日：2005-08-18

申请号：US11052908

申请日：2005-02-09

Applicant: Yasuo Sato ,  Shuji Hamada ,  Toshiyuki Maeda ,  Atsuo Takatori ,  Yasuyuki Nozuyama

Inventor： Yasuo Sato ,  Shuji Hamada ,  Toshiyuki Maeda ,  Atsuo Takatori ,  Yasuyuki Nozuyama

IPC: G01R31/317 ,  G01R31/30 ,  H01L21/66 ,  H01L21/82 ,  G06F19/00

CPC classification number: G01R31/31704 ,  G01R31/3016

Abstract: A circuit quality evaluation method obtains an indicator linked to the quality of a circuit by applying information representing a minimum delay margin of a path passing through an assumed fault site, a machine cycle, and a delay fault occurrence frequency. Further, the circuit quality evaluation method evaluates the quality of the circuit based on the indicator.

Abstract translation: 电路质量评估方法通过应用表示通过假定故障位置的路径的最小延迟余量，机器周期和延迟故障发生频率的信息来获得与电路质量相关联的指示符。 此外，电路质量评估方法基于指示器来评估电路的质量。