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135 条记录 (耗时 0.02 秒)

    Memory system and method of accessing memory chips of a memory system
    71.
    发明申请
    Memory system and method of accessing memory chips of a memory system 失效
    存储器系统和访问存储器系统的存储器芯片的方法

    公开(公告)号：US20060291263A1

    公开(公告)日：2006-12-28

    申请号：US11128789

    申请日：2005-05-13

    申请人： Paul Wallner ,  Ralf Schledz ,  Peter Gregorius ,  Hermann Ruckerbauer

    发明人： Paul Wallner ,  Ralf Schledz ,  Peter Gregorius ,  Hermann Ruckerbauer

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063

    摘要： A memory system and method is disclosed. In one embodiment, the memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.

    摘要翻译： 公开了一种存储器系统和方法。 在一个实施例中，存储器系统包括存储器控制器和至少一个存储器模块，其中一定数量的半导体存储器芯片和连接线被布置在分别指定的拓扑中。 连接线包括形成传输通道的第一连接线，用于基于协议的数据传输和命令信号流从存储器控制器分别存储到存储器模块上的存储器芯片和存储器控制器中的至少一个。 将第二连接线从存储器控制器直接路由到存储器模块上的至少一个存储器芯片，用于将选择信息与数据和命令信号流分离地传送到至少一个存储器芯片。

    Semiconductor memory module
    72.
    发明授权
    Semiconductor memory module 有权
    半导体存储器模块

    公开(公告)号：US07078793B2

    公开(公告)日：2006-07-18

    申请号：US10927312

    申请日：2004-08-27

    申请人： Hermann Ruckerbauer ,  Srdjan Djordjevic

    发明人： Hermann Ruckerbauer ,  Srdjan Djordjevic

    IPC分类号： H01L23/02

    CPC分类号： G11C5/063

    摘要： A semiconductor memory module includes a wiring board in or on which at least a number of data line runs are conducted in a respective width of k bits and which exhibits a number of memory ranks which in each case have n memory chips, and at least one signal driver/control chip (hub), a k-bit-wide data line run in each case connecting a memory chip from each memory rank to the signal driver/control chip (hub) and four or eight memory ranks in each case being arranged distributed on the top and bottom of the wiring board along the associated data line run in such a manner that, in operation, the load is distributed along the respective data line run.

    摘要翻译： 半导体存储器模块包括布线板，其中至少多个数据线运行在k位的相应宽度上，并且具有多个存储器排列，每个存储器级别在每种情况下具有n个存储器芯片，并且至少一个 信号驱动器/控制芯片（集线器），在每种情况下将存储器芯片从每个存储器级连接到信号驱动器/控制芯片（集线器）的k位宽数据线和每个情况下的四个或八个存储器排列被布置 沿着相关联的数据线分布在布线板的顶部和底部，以这样的方式运行：在操作中，负载沿着相应的数据线运行分布。

    Method and apparatus for synchronous signal transmission between at least two logic or memory components
    74.
    发明授权
    Method and apparatus for synchronous signal transmission between at least two logic or memory components 失效
    用于在至少两个逻辑或存储器组件之间同步信号传输的方法和装置

    公开(公告)号：US07043653B2

    公开(公告)日：2006-05-09

    申请号：US10215228

    申请日：2002-08-08

    申请人： Justus Kuhn ,  Hermann Ruckerbauer ,  Frank Thiele

    发明人： Justus Kuhn ,  Hermann Ruckerbauer ,  Frank Thiele

    IPC分类号： G06F1/12

    CPC分类号： G06F1/12

    摘要： An internal clock signal of a logic/memory component that receives signals is transmitted as a reference clock to a transmitting logic/memory component. With the aid of the reference clock, the transmission clock of the output unit of the transmitting logic/memory component is generated, such that transmitted signals arrive in a receiving unit of the receiving component synchronously with the internal clock signal of that component.

    摘要翻译： 将接收信号的逻辑/存储器组件的内部时钟信号作为参考时钟发送到发送逻辑/存储器组件。 借助于参考时钟，产生发送逻辑/存储器部件的输出单元的传输时钟，使得发送的信号与该部件的内部时钟信号同步到达接收部件的接收单元。

    Memory system and method for transferring data therein
    75.
    发明申请
    Memory system and method for transferring data therein 有权
    用于在其中传输数据的存储器系统和方法

    公开(公告)号：US20050041516A1

    公开(公告)日：2005-02-24

    申请号：US10872427

    申请日：2004-06-22

    申请人： Hermann Ruckerbauer

    发明人： Hermann Ruckerbauer

    IPC分类号： G06F11/08 ,  G06F12/16 ,  G06F13/16 ,  G11C7/00 ,  G11C7/10

    CPC分类号： G11C7/1018 ,  G06F13/1684

    摘要： A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to receive, store and transfer data packets to and from a first and second set of memory chips. Transfer of an internal packet data from the control device to memory takes place such that a first record is stored in a second set of memory chips and additional records are stored in the first set of memory chips. In preferred embodiments, data is allocated in the second set of memory chips such that at least one additional transfer step takes place to the second set of memory chips compared with transfers to the first set of memory chips. In the additional transfer step(s), the first set of memory chips is masked from receiving data.

    摘要翻译： 存储器系统在功能上被设计成使得尽管在没有纠错装置的情况下进行操作，但实际提供用于纠错的存储器模块的存储器芯片被同时用于数据传输。 控制装置被配置为接收，存储和传送数据分组到第一和第二组存储器芯片。 将内部分组数据从控制设备传送到存储器进行，使得第一记录被存储在第二组存储器芯片中，并且附加记录被存储在第一组存储器芯片中。 在优选实施例中，在第二组存储器芯片中分配数据，使得与传送到第一组存储器芯片相比，至少一个额外的转移步骤发生到第二组存储器芯片。 在附加传送步骤中，第一组存储器芯片被从接收数据中被掩蔽。

    Method and system including plural memory controllers and a memory access control bus for accessing a memory device
    77.
    发明授权
    Method and system including plural memory controllers and a memory access control bus for accessing a memory device 有权
    包括多个存储器控制器和用于访问存储器件的存储器访问控制总线的方法和系统

    公开(公告)号：US08495310B2

    公开(公告)日：2013-07-23

    申请号：US12235063

    申请日：2008-09-22

    申请人： Peter Gregorius ,  Thomas Hein ,  Martin Maier ,  Hermann Ruckerbauer ,  Thilo Schaffroth ,  Ralf Schedel ,  Wolfgang Spirkl ,  Johannes Stecker

    发明人： Peter Gregorius ,  Thomas Hein ,  Martin Maier ,  Hermann Ruckerbauer ,  Thilo Schaffroth ,  Ralf Schedel ,  Wolfgang Spirkl ,  Johannes Stecker

    IPC分类号： G06F13/36 ,  G06F13/16

    CPC分类号： G06F13/1605 ,  G06F13/1684 ,  Y02D10/14

    摘要： A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration.

    摘要翻译： 系统和方法利用可以经由存储器件的相应端口被多个控制器或处理器核心访问的存储器件。 每个控制器可以经由数据总线耦合到存储器设备的相应端口。 存储器设备的每个端口可以与存储器的预定义部分相关联，从而使每个控制器访问不同部分的存储器，而不受其他控制器的干扰。 公共命令/地址总线可以将多个控制器耦合到存储器设备。 每个控制器可以在存储器访问控制总线上断言有效信号以获得对命令/地址总线的访问以启动存储器访问。 在一些实施例中，多个存储器件可以以堆叠的存储器配置布置在存储器封装中。