公开(公告)号：US11811303B2

公开(公告)日：2023-11-07

申请号：US17485022

申请日：2021-09-24

Applicant: Apple Inc.

Inventor： Chi Nung Ni ,  Sanjay Dabral

IPC: H02M1/15 ,  G06F1/3206 ,  H02M3/158

CPC classification number: H02M1/15 ,  G06F1/3206 ,  H02M3/1582

Abstract: Increases in current drawn from power supply nodes in a computer system can result in unwanted drops in the voltages of the power supply nodes until power supply circuits can compensate for the increased load. To lessen the effects of increases in load currents, a decoupling circuit that includes a diode may be coupled to the power supply node. During a charge mode, a control circuit applies a current to the diode to store charge in the diode. During a boost mode, the control circuit can couple the diode to the power supply node. When the voltage level of the power supply node begins to drop, the diode can source a current to the power supply node using the previously stored charge. The diode may be directly coupled to the power supply node or be part of a switch-based system that employs multiple diodes to increase the discharge voltage.

公开(公告)号：US11699949B2

公开(公告)日：2023-07-11

申请号：US17383983

申请日：2021-07-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Jun Zhai ,  Ralf M. Schmitt ,  Vidhya Ramachandran ,  Wenjie Mao

IPC: H02M3/07 ,  G05F3/10 ,  H01L29/66 ,  H01L23/00 ,  H01L23/522

CPC classification number: H02M3/07 ,  G05F3/10 ,  H01L23/5223 ,  H01L23/5227 ,  H01L24/17 ,  H01L29/66181 ,  H01L2224/02379

Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

公开(公告)号：US20220231687A1

公开(公告)日：2022-07-21

申请号：US17678962

申请日：2022-02-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Bahattin Kilic ,  Jie-Hua Zhao ,  Kunzhong Hu ,  Suk-Kyu Ryu

IPC: H03K19/1776 ,  G06F15/78 ,  H01L23/31 ,  H05K1/02

Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

公开(公告)号：US20220199517A1

公开(公告)日：2022-06-23

申请号：US17133096

申请日：2020-12-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kunzhong Hu ,  Raymundo M. Camenforte

IPC: H01L23/528 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

Abstract: Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.

公开(公告)号：US11309246B2

公开(公告)日：2022-04-19

申请号：US16783132

申请日：2020-02-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18 ,  H01L23/00

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US10714425B2

公开(公告)日：2020-07-14

申请号：US15263632

申请日：2016-09-13

Applicant: Apple Inc.

Inventor： Sanjay Dabral

IPC: H01L23/367 ,  H01L23/34 ,  H01L25/065 ,  H01L23/538 ,  H01L23/427 ,  H01L23/28 ,  H01L23/13 ,  H01L23/00

Abstract: In an embodiment, an interposer includes multiple integrated circuits coupled thereto. The integrated circuits may include processors and non-processor functionality that may have previously been integrated with the processors on an SOC. By separating the functionality into multiple integrated circuits, the integrated circuits may be arranged on the interposer to spread out the potentially high power ICs and lower power ICs, interleaving them. In other embodiments, instances of the integrated circuits (e.g. processors) from different manufacturing process conditions may be selected to allow a mix of high performance, high power density integrated circuits and lower performance, low power density integrated circuits. In an embodiment, a phase change material may be in contact with the integrated circuits, providing a local reservoir to absorb heat. In an embodiment, a battery or display components may increase thermal mass and allow longer optimal performance state operation.

公开(公告)号：US20200075497A1

公开(公告)日：2020-03-05

申请号：US16583082

申请日：2019-09-25

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai

IPC: H01L23/538 ,  H01L23/488 ,  H01L23/00 ,  H01L25/18 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

公开(公告)号：US10566286B2

公开(公告)日：2020-02-18

申请号：US16250854

申请日：2019-01-17

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Huabo Chen ,  Zhenggang Cheng

IPC: H01L23/52 ,  H01L23/538 ,  H01L23/498 ,  H01L23/14 ,  H01L23/00 ,  H01L25/065

Abstract: Routing structures including signal routing between die areas is described. In an embodiment, routing structures include signal lines with a characteristic thickness that is greater than a width. The signal lines may be twisted, and run directly underneath pads.

公开(公告)号：US10438896B2

公开(公告)日：2019-10-08

申请号：US15801163

申请日：2017-11-01

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zun Zhai

IPC: H01L23/48 ,  H01L21/44 ,  H01L23/538 ,  H01L23/488 ,  H01L23/00 ,  H01L25/18 ,  H01L23/522 ,  H01L23/58 ,  H01L21/66 ,  H01L23/528

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

公开(公告)号：US09509490B1

公开(公告)日：2016-11-29

申请号：US14859757

申请日：2015-09-21

Applicant: Apple Inc.

Inventor： Sanjay Dabral

IPC: H04L25/49 ,  H04L25/40 ,  H03D3/24 ,  H04L7/033 ,  H03L7/099

CPC classification number: H04L7/0008 ,  G06F1/04 ,  H03L7/16 ,  H04L7/0091

Abstract: A system for sharing a reference clock signal between multiple devices is disclosed. The system includes a source device, and a plurality of destination devices. The source device may be configured to generate a reference clock signal and transmit data via a communication link. The reference clock signal may include first and second phases, and the second phase may be an inverse of the first phase. A filter unit configured to filter the reference clock signal may be coupled between the first and second phases of the reference clock signal. Each destination device may be configured to receive the reference clock signal and receive the data dependent upon the reference clock signal.

Abstract translation: 公开了一种用于在多个设备之间共享参考时钟信号的系统。 该系统包括源设备和多个目的设备。 源设备可以被配置为生成参考时钟信号并且经由通信链路发送数据。 参考时钟信号可以包括第一和第二相位，第二相位可以是第一相位的倒数。 被配置为对参考时钟信号进行滤波的滤波器单元可以耦合在参考时钟信号的第一和第二相位之间。 每个目的地设备可以被配置为接收参考时钟信号并且接收依赖于参考时钟信号的数据。