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71.发明授权公开(公告)号：US07589384B2
公开(公告)日：2009-09-15
申请号：US11404075
申请日：2006-04-14
申请人： Atsuhiro Kinoshita
发明人： Atsuhiro Kinoshita
IPC分类号： H01L23/62
CPC分类号： H01L27/0251 , H01L29/665 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： It is made possible to easily set a protection voltage even when a semiconductor device to be protected includes a gate insulating film having a low dielectric breakdown voltage. A semiconductor device includes: a MOS transistor including a first gate insulating film provided on a first element region of first conductivity-type in a semiconductor, a first gate electrode provided on the first gate insulating film, and first impurity regions of second conductivity-type provided in the first element region on both sides of the first gate electrode; and an ESD protection element including a second gate insulating film provided on a second element region of first conductivity-type in the semiconductor substrate and having substantially the same thickness as the first gate insulating film, a second gate electrode provided on the second gate insulating film and connected to the first gate electrode, and second impurity regions of second conductivity-type provided in the second element region on both sides of the second gate electrode.
摘要翻译： 即使要被保护的半导体器件包括具有低介电击穿电压的栅极绝缘膜，也可以容易地设定保护电压。 半导体器件包括：MOS晶体管，包括设置在半导体中的第一导电类型的第一元件区域上的第一栅极绝缘膜，设置在第一栅极绝缘膜上的第一栅极电极和第二导电类型的第一杂质区域 设置在所述第一栅电极的两侧的所述第一元件区域中; 以及ESD保护元件，包括设置在半导体衬底中的第一导电类型的第二元件区上并具有与第一栅极绝缘膜基本相同的厚度的第二栅极绝缘膜，设置在第二栅极绝缘膜上的第二栅电极 并且连接到第一栅电极，以及设置在第二栅电极两侧的第二元件区中的第二导电类型的第二杂质区。
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公开(公告)号：US07589381B2
公开(公告)日：2009-09-15
申请号：US11519794
申请日：2006-09-13
申请人： Atsuhiro Kinoshita , Junji Koga
发明人： Atsuhiro Kinoshita , Junji Koga
IPC分类号： H01L47/00
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/458 , H01L29/6653 , H01L29/6659 , H01L29/66643 , H01L29/66772 , H01L29/66795 , H01L29/7833 , H01L29/7839 , H01L29/78618 , H01L29/78645
摘要： A field effect transistor includes a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region, source and drain electrodes formed to sandwich the first semiconductor region in a channel lengthwise direction, and second semiconductor regions formed between the first semiconductor region and the source and drain electrodes and having impurity concentration higher than the first semiconductor region. The thickness of the second semiconductor region in the channel lengthwise direction is set to a value equal to or less than depletion layer width determined by the impurity concentration so that the second semiconductor region is depleted in a no-voltage application state.
摘要翻译： 场效应晶体管包括形成沟道区域的第一半导体区域，绝缘地设置在第一半导体区域上方的栅电极，形成为在沟道纵向方向夹着第一半导体区域的源电极和漏电极，以及形成在第一半导体区域之间的第二半导体区域 半导体区域和源极和漏极，并且具有高于第一半导体区域的杂质浓度。 通道长度方向上的第二半导体区域的厚度被设定为等于或小于由杂质浓度确定的耗尽层宽度的值，使得第二半导体区域在无电压施加状态下耗尽。
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公开(公告)号：US07521752B2
公开(公告)日：2009-04-21
申请号：US11384269
申请日：2006-03-21
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823437 , H01L21/84 , H01L27/1203 , H01L29/41733 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L29/78618
摘要： It is possible to reliably implant an impurity into an impurity forming region, and to form a self-aligned silicides on the entire portion of the source and drain regions. There are provided: a first semiconductor layer of a first conductivity type in a substantially a rectangular solid shape formed on a substrate; a gate electrode formed on a pair of first side portions of the first semiconductor layer facing to each other with a gate insulating film being placed between the gate electrode and the first side portions; a second semiconductor layer of the first conductivity type connected to bottom portions of a pair of second side portions of the first semiconductor layer placed in a substantially perpendicular direction with respect to the first side portions, the second semiconductor layer extending along the substantially perpendicular direction; a first impurity region of a second conductivity type formed in the second semiconductor layer; second impurity regions formed on the pair of side portions of the first semiconductor layer and connected to the first impurity region; and a channel region formed between the second impurity regions of the first semiconductor layer.
摘要翻译： 可以将杂质可靠地注入到杂质形成区域中，并且在源极和漏极区域的整个部分上形成自对准的硅化物。 提供：形成在基板上的基本为矩形的实心形状的第一导电类型的第一半导体层; 形成在所述第一半导体层的一对第一侧部分上的栅电极，栅极绝缘膜位于所述栅电极和所述第一侧部之间，所述栅极绝缘膜彼此面对; 所述第一导电类型的第二半导体层连接到所述第一半导体层的一对第二侧部的与所述第一侧部大致垂直的方向上的第二侧部的底部，所述第二半导体层沿着大致垂直的方向延伸; 形成在第二半导体层中的第二导电类型的第一杂质区; 第二杂质区，形成在第一半导体层的一对侧部并连接到第一杂质区; 以及形成在第一半导体层的第二杂质区之间的沟道区。
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公开(公告)号：US07514753B2
公开(公告)日：2009-04-07
申请号：US11761288
申请日：2007-06-11
IPC分类号： H01L29/76
CPC分类号： H01L29/4908 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/4975 , H01L29/517 , H01L29/66643 , H01L29/785
摘要： A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain regions formed opposite to each other interposing the n-channel region therebetween, a first gate insulator formed on the n-channel region, and a first gate electrode formed on the first gate insulator and including a compound of a metal M and a first group-IV elements Si1-a Gea (0≦a≦1), the p-type device including a p-channel region formed on the substrate, p-type source and drain regions formed opposite to each other interposing the p-channel region therebetween, a second gate insulator formed on the p-channel region, and a second gate electrode formed on the second gate insulator, and including a compound of the metal M and a second group-IV element Si1-c Gec (0≦c≦1, a≠c).
摘要翻译： 半导体器件包括形成在衬底上的n型和p型半导体器件，n型器件包括形成在衬底上的n沟道区，n型源极和漏极区彼此相对形成， 沟道区域，形成在n沟道区上的第一栅极绝缘体和形成在第一栅极绝缘体上的第一栅电极，并且包括金属M和第一族IV族元素Si1-a Gea（0≤...） a <= 1），所述p型器件包括形成在所述衬底上的p沟道区，形成在所述p沟道区之间的彼此相对形成的p型源极和漏极区，形成在所述p上的第二栅极绝缘体 以及形成在第二栅极绝缘体上的第二栅电极，并且包括金属M和第二IV族元素Si1-c Gec（0≤c≤1，a≤c）的化合物。
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75.发明申请公开(公告)号：US20090008726A1
公开(公告)日：2009-01-08
申请号：US12051947
申请日：2008-03-20
申请人： Takashi Yamauchi , Yoshifumi Nishi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato
发明人： Takashi Yamauchi , Yoshifumi Nishi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato
IPC分类号： H01L47/00 , H01L21/425
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823821 , H01L21/823835 , H01L21/823842 , H01L29/785
摘要： A method of manufacturing a semiconductor device reducing interface resistance of n-type and p-type MISFETs are provided. According to the method, a gate dielectric film and a gate electrode of the n-type MISFET are formed on a first semiconductor region, a gate dielectric film and a gate electrode of the p-type MISFET are formed on a second semiconductor region, an n-type diffusion layer is formed by ion implantation of As into the first semiconductor region, a first silicide layer is formed by first heat treatment after a first metal containing Ni is deposited on the n-type diffusion layer, the first silicide layer is made thicker by second heat treatment after a second metal containing Ni is deposited on the first silicide layer and second semiconductor region, and third heat treatment is provided after formation of a second silicide layer and ion implantation of B or Mg into the second silicide layer.
摘要翻译： 提供了制造半导体器件降低n型和p型MISFET的界面电阻的方法。 根据该方法，在第一半导体区域上形成栅极电介质膜和n型MISFET的栅电极，在第二半导体区域上形成p型MISFET的栅极电介质膜和栅电极， 通过将As离子注入第一半导体区域形成n型扩散层，在n型扩散层上沉积含有Ni的第一金属之后，通过第一热处理形成第一硅化物层，制作第一硅化物层 在第一硅化物层和第二半导体区域上沉积含有Ni的第二金属沉积第二热处理之后，在形成第二硅化物层和在第二硅化物层中离子注入B或Mg之后提供第三热处理。
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76.发明申请公开(公告)号：US20080308877A1
公开(公告)日：2008-12-18
申请号：US12193668
申请日：2008-08-18
IPC分类号： H01L27/08
CPC分类号： H01L21/28105 , H01L21/28097 , H01L21/32155 , H01L21/82385 , H01L29/66651 , H01L29/785
摘要： A semiconductor device includes a semiconductor substrate; a first gate insulation film formed on the semiconductor substrate; a second gate insulation film formed on the semiconductor substrate; a first gate electrode formed on the first gate insulation film and fully silicided; and a second gate electrode formed on the second gate insulation film and fully silicided, a gate length or a gate width of the second gate electrode being larger than that of the first gate electrode, and a thickness of the second gate electrode being smaller than that of the first gate electrode.
摘要翻译： 半导体器件包括半导体衬底; 形成在所述半导体基板上的第一栅极绝缘膜; 形成在所述半导体基板上的第二栅极绝缘膜; 形成在第一栅极绝缘膜上并完全硅化的第一栅电极; 以及形成在所述第二栅极绝缘膜上并完全硅化的第二栅电极，所述第二栅电极的栅极长度或栅极宽度大于所述第一栅电极的栅极长度或栅极宽度，并且所述第二栅电极的厚度小于所述第二栅电极的厚度 的第一栅电极。
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公开(公告)号：US20080237655A1
公开(公告)日：2008-10-02
申请号：US12053873
申请日：2008-03-24
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78639
摘要： A semiconductor apparatus includes: a support substrate made of a semiconductor; an insulating layer provided on the support substrate and having a first and a second openings; a semiconductor fin having a channel section, a first and second buried regions, a source section and a drain section; a gate insulating film covering a side face of the channel section; and a gate electrode opposed to the side face of the channel section across the gate insulating film. The channel section is provided upright on the insulating layer between the first and the second openings. The first and the second buried regions are provided in the first and the second openings on both sides of the channel section. The source-drain sections are provided on the first and the second buried regions and connected to the channel section.
摘要翻译： 半导体装置包括：由半导体制成的支撑基板; 绝缘层，设置在所述支撑基板上并且具有第一和第二开口; 具有通道部分，第一和第二掩埋区域，源极部分和漏极部分的半导体鳍片; 覆盖所述通道部分的侧面的栅极绝缘膜; 以及栅极电极，与栅极绝缘膜的沟道部分的侧面相对。 通道部分直立地设置在第一和第二开口之间的绝缘层上。 第一和第二掩埋区域设置在通道部分两侧的第一和第二开口中。 源极 - 漏极部分设置在第一和第二埋置区域上并且连接到沟道部分。
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公开(公告)号：US20080227241A1
公开(公告)日：2008-09-18
申请号：US12043327
申请日：2008-03-06
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/845 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795
摘要： A semiconductor device fabrication method for forming on a wafer-bonded substrate p- and n-type FinFETs each having a channel plane exhibiting high carrier mobility is disclosed. First, prepare two semiconductor wafers. Each wafer has a surface of {100} crystalline orientation and a direction. These wafers are surface-bonded together so that the directions of upper and lower wafers cross each other at a rotation angle, thereby providing a “hybrid” crystal-oriented substrate. On this substrate, form semiconductor regions, one of which is identical in direction to the upper wafer, and the other of which is equal in direction to the lower wafer. In the one region, form a pFinFET having {100} channel plane. In the other region, form an nFinFET having its channel direction in parallel or perpendicular to that of the pFinFET. A CMOS FinFET structure is thus obtained.
摘要翻译： 公开了一种半导体器件制造方法，用于在晶片结合的衬底上形成各自具有表现出高载流子迁移率的沟道平面的p型和n型FinFET。 首先，准备两个半导体晶圆。 每个晶片具有{100}晶体取向和<110>方向的表面。 这些晶片被表面粘合在一起，使得上下晶片的<110>方向以旋转角彼此交叉，从而提供“混合”的晶体取向基板。 在该衬底上，形成半导体区域，其中一个在<110>方向上与上晶片相同，另一个在<110>方向与下晶片相等。 在一个区域中，形成具有{100}通道平面的pFinFET。 在另一区域，形成其通道方向平行或垂直于pFinFET的nFinFET。 由此获得CMOS FinFET结构。
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公开(公告)号：US07343263B2
公开(公告)日：2008-03-11
申请号：US11469706
申请日：2006-09-01
IPC分类号： G04F10/00
CPC分类号： G04F10/10
摘要： An electronic timer having a parallel unit, a current detecting unit, and a time measuring unit. The parallel unit is formed of a plurality of aging devices connected in parallel and configured to be turned on or off for a predetermined time after storing electric charges. Each aging device is a transistor which includes a floating gate. The current detecting unit detects a sum current flowing in the parallel unit when a voltage is applied between input and output terminals of the parallel unit. The time measuring unit measures a time required to resume the supplying of power after the interruption of power supplying, from the sum current detected by the current detecting unit.
摘要翻译： 具有并联单元，电流检测单元和时间测量单元的电子计时器。 并联单元由并联连接的多个老化装置形成，并且在存储电荷之后被配置为开启或关闭预定时间。 每个老化装置是包括浮动栅极的晶体管。 当在并行单元的输入和输出端之间施加电压时，电流检测单元检测在并联单元中流动的和电流。 所述时间测量单元根据由所述电流检测单元检测到的和电流来测量在供电中断之后恢复供电所需的时间。
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公开(公告)号：US20050127451A1
公开(公告)日：2005-06-16
申请号：US10997939
申请日：2004-11-29
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/76
CPC分类号： H01L29/4908 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/4975 , H01L29/517 , H01L29/66643 , H01L29/785
摘要： A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain regions formed opposite to each other interposing the n-channel region therebetween, a first gate insulator formed on the n-channel region, and a first gate electrode formed on the first gate insulator and including a compound of a metal M and a first group-IV elements Si1−a Gea (0≦a≦1), the p-type device including a p-channel region formed on the substrate, p-type source and drain regions formed opposite to each other interposing the p-channel region therebetween, a second gate insulator formed on the p-channel region, and a second gate electrode formed on the second gate insulator, and including a compound of the metal M and a second group-IV element Si1−c Gec (0≦c≦1, a≠c).
摘要翻译： 半导体器件包括形成在衬底上的n型和p型半导体器件，n型器件包括形成在衬底上的n沟道区，n型源极和漏极区彼此相对形成， 沟道区域，形成在n沟道区上的第一栅极绝缘体和形成在第一栅极绝缘体上的第一栅电极，并且包括金属M和第一族IV元素Si 1-a的化合物， （0 <= a <= 1），p型器件包括形成在衬底上的p沟道区域，彼此相对形成的p型源极和漏极区域 在其间插入p沟道区域，形成在p沟道区域上的第二栅极绝缘体和形成在第二栅极绝缘体上的第二栅电极，并且包括金属M和第二IV族元素Si c）。
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