公开(公告)号：US5128230A

公开(公告)日：1992-07-07

申请号：US644752

申请日：1991-01-23

申请人： Michael K. Templeton ,  Anthony Zampini ,  Peter Trefonas, III ,  James C. Woodbrey ,  David C. Madoux ,  Brian K. Daniels

发明人： Michael K. Templeton ,  Anthony Zampini ,  Peter Trefonas, III ,  James C. Woodbrey ,  David C. Madoux ,  Brian K. Daniels

IPC分类号： G03F7/004 ,  G03F7/022

CPC分类号： G03F7/0226 ,  G03F7/0048

摘要： This invention is directed to novel photoresist processes and compositions having high resolution novalac resins, high resolution photoactive components with several diazoquinone groups per molecule, and solvents having a high solvency power, better safety, improved photospeed, higher contrast and equivalent cast film thickness from lower percent solids formulations.

摘要翻译： 本发明涉及具有高分辨率诺瓦克树脂的新型光刻胶工艺和组合物，每分子具有几个重氮醌基团的高分辨率光活性组分和具有高偿付能力的溶剂，更好的安全性，更高的感光速度，更高的对比度和相当的流延膜厚度从较低 固含量百分数。

公开(公告)号：US06603211B2

公开(公告)日：2003-08-05

申请号：US09784907

申请日：2001-02-15

申请人： Michael K. Templeton ,  Hao Fang ,  Maria C. Chan ,  King Wai Kelwin Ko

发明人： Michael K. Templeton ,  Hao Fang ,  Maria C. Chan ,  King Wai Kelwin Ko

IPC分类号： H01L23544

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and system for providing an alignment mark for a thin layer in a semiconductor device is disclosed. The semiconductor device includes at least one alternative part having a first thickness greater than a second thickness of the thin layer. The method and system include providing the thin layer and providing the alignment mark for the thin layer in the at least one alternative part. The alignment mark has a depth that is greater than the second thickness of the thin layer. In one aspect, the method and system include providing a mask for the thin layer. The mask includes an alignment mark portion that covers the at least one alternative part and that is for providing the alignment mark. In this aspect, the method and system also include removing a portion of the at least one alternative part to provide the alignment mark in the at least one alternative part.

公开(公告)号：US06495435B2

公开(公告)日：2002-12-17

申请号：US09788246

申请日：2001-02-15

申请人： Michael K. Templeton ,  Hao Fang ,  Maria C. Chan

发明人： Michael K. Templeton ,  Hao Fang ,  Maria C. Chan

IPC分类号： H01L2120

CPC分类号： H01L27/11521 ,  H01L21/76838 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115

摘要： A method and system for providing a plurality of lines in a semiconductor memory device is disclosed. The method and system include providing a semiconductor substrate, providing a plurality of lines and providing an adjacent feature. The plurality of lines includes an adjacent line adjacent to the adjacent feature. The each of the plurality of lines has a line width that is substantially the same for each of the plurality of lines. The plurality of lines is preferably formed utilizing a mask to print a physical mask for the plurality of lines and the adjacent feature. The mask includes a mask assist feature between at least a first polygon for the adjacent line and at least a second polygon for the adjacent feature. The mask assist feature has a size that is sufficiently large to affect the width of the adjacent line and that is sufficiently small to prevent a corresponding feature from being printed on the physical mask. The method and system also preferably include removing a second portion of the layer of material exposed by the pattern of the physical mask to form the plurality of lines.

摘要翻译： 公开了一种用于在半导体存储器件中提供多条线的方法和系统。 该方法和系统包括提供半导体衬底，提供多条线并提供相邻特征。 多条线包括与相邻特征相邻的相邻线。 多条线中的每条线具有对于多根线中的每条线基本相同的线宽度。 优选地，利用掩模形成多条线以打印多条线和相邻特征的物理掩模。 掩模包括用于相邻行的至少第一多边形和用于相邻特征的至少第二多边形之间的掩模辅助特征。 掩模辅助特征具有足够大的尺寸以影响相邻线的宽度，并且足够小以防止相应的特征被印刷在物理掩模上。 该方法和系统还优选地包括去除由物理掩模的图案暴露的材料层的第二部分以形成多条线。

公开(公告)号：US06445051B1

公开(公告)日：2002-09-03

申请号：US09563797

申请日：2000-05-02

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko ,  John Jianshi Wang ,  Michael K. Templeton ,  Lu You ,  Angela T. Hui

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko ,  John Jianshi Wang ,  Michael K. Templeton ,  Lu You ,  Angela T. Hui

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L21/28273

摘要： A method and system for providing a plurality of contacts in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and a plurality of field insulating regions adjacent to a portion of the plurality of gate stacks. The method and system include providing an etch stop layer covering the plurality of field insulating regions. The etch stop layer has an etch selectivity different from a field insulating region etch selectivity of the plurality of field insulating regions. The method and system also include providing an insulating layer covering the plurality of gate stacks, the plurality of field insulating regions and the etch stop layer. The method and system further include etching the insulating layer to provide a plurality of contact holes. The insulating layer etching step uses the etch stop layer to ensure that the insulating etching step does not etch through the plurality of field insulating regions. The method and system also include filling the plurality of contact holes with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供多个触点的方法和系统。 闪存器件包括多个栅极堆叠和与多个栅极堆叠的一部分相邻的多个场绝缘区域。 该方法和系统包括提供覆盖多个场绝缘区域的蚀刻停止层。 蚀刻停止层具有与多个场绝缘区域的场绝缘区蚀刻选择性不同的蚀刻选择性。 该方法和系统还包括提供覆盖多个栅极叠层，多个场绝缘区域和蚀刻停止层的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供多个接触孔。 绝缘层蚀刻步骤使用蚀刻停止层来确保绝缘蚀刻步骤​​不会蚀刻穿过多个场绝缘区域。 该方法和系统还包括用导体填充多个接触孔。

公开(公告)号：US06316804B1

公开(公告)日：2001-11-13

申请号：US09569721

申请日：2000-05-11

申请人： Michael K. Templeton ,  Kathleen R. Early

发明人： Michael K. Templeton ,  Kathleen R. Early

IPC分类号： H01L29788

CPC分类号： H01L27/11521

摘要： A semiconductor apparatus and fabrication method for forming oxide isolation regions in a semiconductor substrate for use in forming self-aligned, floating gate MOS structures or other semiconductor devices. The method includes providing a semiconductor substrate member prefabricated having a barrier oxide layer, a polysilicon layer and a plurality of spaced apart silicon nitride layer portions fabricated on the polysilicon layer. The nitride layer portions delineate regions for forming the self-aligned floating gate MOS structures, as well as delineating portions of the silicon dioxide layer and portions of said polysilicon layer that are unprotected by the plurality of silicon nitride layer portions. The method further includes the step of implanting oxygen O2 ions into regions of the substrate, including those unprotected portions of the silicon dioxide layer and portions of the polysilicon layer to form the oxide isolation regions. After removing the silicon nitride layer portions, and exposing the polysilicon layer portions, the implanted structure is annealed and made ready for forming the self-aligned floating gate MOS structures, or other semiconductor structure on the conductive material pads. The floating gates may be formed having a minimal width with respect to an underlying active region.

摘要翻译： 一种半导体装置和制造方法，用于在用于形成自对准的浮置栅极MOS结构或其它半导体器件的半导体衬底中形成氧化物隔离区。 该方法包括提供预制的半导体衬底构件，其具有制造在多晶硅层上的阻挡氧化物层，多晶硅层和多个间隔开的氮化硅层部分。 氮化物层部分描绘用于形成自对准浮置栅极MOS结构的区域，以及描绘未被多个氮化硅层部分保护的二氧化硅层的部分和所述多晶硅层的部分。 该方法还包括将氧O 2离子注入到衬底的区域中的步骤，包括二氧化硅层的那些未受保护的部分和多晶硅层的部分以形成氧化物隔离区。 在去除氮化硅层部分并暴露多晶硅层部分之后，将注入结构退火并准备好在导电材料焊盘上形成自对准浮栅MOS结构或其它半导体结构。 浮动栅极可以形成为相对于下面的有源区域具有最小宽度。

公开(公告)号：US6093967A

公开(公告)日：2000-07-25

申请号：US992573

申请日：1997-12-17

申请人： Yowjuang W. Liu ,  Mark S. Chang ,  Michael K. Templeton

发明人： Yowjuang W. Liu ,  Mark S. Chang ,  Michael K. Templeton

IPC分类号： H01L21/285 ,  H01L23/54 ,  H01L21/441

CPC分类号： H01L21/28518

摘要： Self-aligned silicide contacts having a height that is at least about equal to the gate height are formed by depositing silicon over active regions of the substrate, depositing a refractory metal over the silicon, and heating the silicon and the refractory metal. The deposited silicon may be amorphous silicon in which case the deposition temperature can be as low as 580.degree. C. If polysilicon is deposited, the deposition temperature has to be at least 620.degree. C.

摘要翻译： 通过在衬底的有源区上沉积硅，在硅上沉积难熔金属，并加热硅和难熔金属，形成具有至少约等于栅极高度的高度的自对准硅化物触点。 沉积的硅可以是非晶硅，在这种情况下，沉积温度可以低至580℃。如果沉积多晶硅，则沉积温度必须至少为620℃。

公开(公告)号：US6066530A

公开(公告)日：2000-05-23

申请号：US57992

申请日：1998-04-09

申请人： Michael K. Templeton ,  Kathleen R. Early

发明人： Michael K. Templeton ,  Kathleen R. Early

IPC分类号： H01L21/8247 ,  H01L21/336

CPC分类号： H01L27/11521

摘要： A semiconductor apparatus and fabrication method for forming oxide isolation regions in a semiconductor substrate for use in forming self-aligned, floating gate MOS structures or other semiconductor devices. The method includes providing a semiconductor substrate member prefabricated having a barrier oxide layer, a polysilicon layer and a plurality of spaced apart silicon nitride layer portions fabricated on the polysilicon layer. The nitride layer portions delineate regions for forming the self-aligned floating gate MOS structures, as well as delineating portions of the silicon dioxide layer and portions of said polysilicon layer that are unprotected by the plurality of silicon nitride layer portions. The method further includes the step of implanting oxygen O.sub.2 ions into regions of the substrate, including those unprotected portions of the silicon dioxide layer and portions of the polysilicon layer to form the oxide isolation regions. After removing the silicon nitride layer portions, and exposing the polysilicon layer portions, the implanted structure is annealed and made ready for forming the self-aligned floating gate MOS structures, or other semiconductor structure on the conductive material pads. The floating gates may be formed having a minimal width with respect to an underlying active region.

摘要翻译： 一种半导体装置和制造方法，用于在用于形成自对准的浮置栅极MOS结构或其它半导体器件的半导体衬底中形成氧化物隔离区。 该方法包括提供预制的半导体衬底构件，其具有制造在多晶硅层上的阻挡氧化物层，多晶硅层和多个间隔开的氮化硅层部分。 氮化物层部分描绘用于形成自对准浮置栅极MOS结构的区域，以及描绘未被多个氮化硅层部分保护的二氧化硅层的部分和所述多晶硅层的部分。 该方法还包括将氧O 2离子注入到衬底的区域中的步骤，包括二氧化硅层的那些未受保护的部分和多晶硅层的部分以形成氧化物隔离区。 在去除氮化硅层部分并暴露多晶硅层部分之后，将注入结构退火并准备好在导电材料焊盘上形成自对准浮栅MOS结构或其它半导体结构。 浮动栅极可以形成为相对于下面的有源区域具有最小宽度。

公开(公告)号：US06834158B1

公开(公告)日：2004-12-21

申请号：US09951473

申请日：2001-09-13

申请人： Michael K. Templeton

发明人： Michael K. Templeton

IPC分类号： F26B330

CPC分类号： B82Y15/00 ,  G03F7/40

摘要： According to one aspect of the present invention, pinhole defects in resist coatings are repaired by heating the resist briefly to induce the resist to flow and fill pinholes. The resist is brought to a temperature at or above that at which the resist flows for long enough to permit the resist to flow and fill pinhole defects, but not so long as to corrupt the resist pattern. The original resist pattern may be biased to allow for some flow during the pinhole repair process. The entire patterned resist may be heated at once, or it may be heated one portion at a time. The application of heat may optionally be limited to locations where pinhole defects are found. By means of the invention, very thin patterned resist coatings free from pinhole defects may be obtained.

摘要翻译： 根据本发明的一个方面，抗蚀剂涂层中的针孔缺陷通过短暂加热抗蚀剂来引起抗蚀剂流动和填充针孔而被修复。 使抗蚀剂达到等于或高于抗蚀剂流动的温度足够长以允许抗蚀剂流动并填充针孔缺陷，但不会损坏抗蚀剂图案。 原始抗蚀剂图案可能被偏压以允许针孔修复过程中的一些流动。 整个图案化的抗蚀剂可以一次加热，或者可以一次加热一部分。 热的应用可以可选地限于找到针孔缺陷的位置。 通过本发明，可以获得非常薄的图案化抗蚀剂涂层，其不存在针孔缺陷。

公开(公告)号：US06830389B2

公开(公告)日：2004-12-14

申请号：US09973034

申请日：2001-10-09

申请人： Michael K. Templeton

发明人： Michael K. Templeton

IPC分类号： G03B500

CPC分类号： G03F7/3007

摘要： A system and method is provided for applying a developer to a photoresist material layer disposed on a semiconductor substrate. The developer system and method employ a developer plate having a plurality of a apertures for dispensing developer. Preferably, the developer plate has a bottom surface with a shape that is similar to the wafer. The developer plate is disposed above the wafer and substantially and/or completely surrounds the top surface of the wafer during application of the developer. A small gap is formed between the wafer and the bottom surface of the developer plate. The wafer and the developer plate form a parallel plate pair, such that the gap can be made small enough so that the developer fluid quickly fills the gap. A differential voltage is applied to the developer plate and the wafer causing an electric field to be formed in the gap. Transportation of negatively charge photoresist material is facilitated by exposure to the electric field during the development process.

摘要翻译： 提供了一种用于将显影剂施加到设置在半导体衬底上的光致抗蚀剂材料层的系统和方法。 显影剂系统和方法采用具有多个用于分配显影剂的孔的显影剂板。 优选地，显影剂板具有与晶片类似的形状的底表面。 显影剂板设置在晶片上方并且在施加显影剂的过程中基本上和/或完全地包围晶片的顶表面。 在晶片和显影剂板的底表面之间形成小的间隙。 晶片和显影剂板形成平行板对，使得间隙可以制得足够小，使得显影剂流体快速填充间隙。 对显影剂板和晶片施加差分电压，从而在间隙中形成电场。 在显影过程中通过暴露于电场来促进负电荷光致抗蚀剂材料的传输。

公开(公告)号：US06752899B1

公开(公告)日：2004-06-22

申请号：US10050499

申请日：2002-01-16

申请人： Bhanwar Singh ,  Arvind Halliyal ,  Michael K. Templeton

发明人： Bhanwar Singh ,  Arvind Halliyal ,  Michael K. Templeton

IPC分类号： H01L2100

CPC分类号： H01L21/67253 ,  C23C14/545 ,  C23C16/52

摘要： The invention provides a system and process for depositing films, wherein an acoustic microbalance is used for process monitoring and/or control. The acoustic microbalance is placed in a deposition chamber and may optionally be mounted on a semiconductor substrate, such as a silicon wafer, on which a film is being deposited. Data from the acoustic microbalance is employed to detect a process endpoint, determine an adjustment to process conditions for a subsequent batch, and/or provide feedback control over current process conditions. One aspect of the invention involves the application of a model or database to correct for differences between the extent of deposition on an acoustic microbalance cantilever and the extent of deposition on a substrate being processed. Another aspect of the invention takes a probabilistic approach to employing acoustic microbalance data. The acoustic microbalance data is employed, optionally together with other process data, as evidence in a probabilistic dependancy model that infers the process state and/or predicts a process outcome.

摘要翻译： 本发明提供一种用于沉积膜的系统和方法，其中使用声学微量天平进行过程监测和/或控制。 声学微量天平被放置在沉积室中，并且可以可选地安装在其上沉积有膜的半导体衬底（例如硅晶片）上。 来自声学微量天平的数据用于检测过程终点，确定对后续批次的处理条件的调整，和/或提供关于当前工艺条件的反馈控制。 本发明的一个方面涉及应用模型或数据库来校正声学微平衡悬臂上的沉积程度与正在处理的基底上的沉积程度之间的差异。 本发明的另一方面采用使用声学微量天平数据的概率方法。 声学微量天平数据可选地与其他过程数据一起被用作推理过程状态和/或预测过程结果的概率依赖模型中的证据。