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公开(公告)号：US20120327555A1
公开(公告)日：2012-12-27
申请号：US13529766
申请日：2012-06-21
申请人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Young Hoon Song , Mi Hee Lee
发明人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Young Hoon Song , Mi Hee Lee
IPC分类号： H01G4/12
摘要： There is provided a chip type laminated capacitor, including: a ceramic body including a dielectric layer having a thickness equal to 10 or more times an average particle diameter of a grain included therein and being 3 □m or less; first and second outer electrodes formed on both ends of the ceramic body in a length direction; first and second band parts formed to extend inwardly of the ceramic body in the length direction on a length-width (L-W) plane from the first and second outer electrodes and having different lengths; and third and fourth band parts formed to extend inwardly of the ceramic body in the length direction on a length-thickness (L-T) plane from the first and second outer electrodes and having different lengths.
摘要翻译： 提供了一种片式叠层电容器，其包括：陶瓷体，其包括厚度等于其中包含的晶粒的平均粒径的10倍以上且为3μm以下的电介质层; 第一外电极和第二外电极，其在长度方向上形成在陶瓷体的两端; 第一和第二带部分形成为在第一和第二外部电极的长度（L-W）平面上沿长度方向在陶瓷体的内部延伸并具有不同的长度; 以及第三和第四带部分，其形成为在长度方向上在距第一和第二外部电极的长度 - 厚度（L-T）平面上延伸到陶瓷体的内侧并具有不同的长度。
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公开(公告)号：US08385048B2
公开(公告)日：2013-02-26
申请号：US13529766
申请日：2012-06-21
申请人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Young Hoon Song , Mi Hee Lee
发明人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Young Hoon Song , Mi Hee Lee
IPC分类号： H01G4/06
摘要： There is provided a chip type laminated capacitor, including: a ceramic body including a dielectric layer having a thickness equal to 10 or more times an average particle diameter of a grain included therein and being 3 □m or less; first and second outer electrodes formed on both ends of the ceramic body in a length direction; first and second band parts formed to extend inwardly of the ceramic body in the length direction on a length-width (L-W) plane from the first and second outer electrodes and having different lengths; and third and fourth band parts formed to extend inwardly of the ceramic body in the length direction on a length-thickness (L-T) plane from the first and second outer electrodes and having different lengths.
摘要翻译： 提供了一种片式叠层电容器，其包括：陶瓷体，其包括厚度等于其中包含的晶粒的平均粒径的10倍以上且为3μm以下的电介质层; 第一外电极和第二外电极，其在长度方向上形成在陶瓷体的两端; 第一和第二带部分形成为在第一和第二外部电极的长度（L-W）平面上沿长度方向在陶瓷体的内部延伸并具有不同的长度; 以及第三和第四带部分，其形成为在长度方向上在距第一和第二外部电极的长度 - 厚度（L-T）平面上延伸到陶瓷体的内侧并具有不同的长度。
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公开(公告)号：US08351181B1
公开(公告)日：2013-01-08
申请号：US13531242
申请日：2012-06-22
申请人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Young Hoon Song , Mi Hee Lee
发明人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Young Hoon Song , Mi Hee Lee
IPC分类号： H01G4/06
摘要： There is provided a chip type laminated capacitor including: a ceramic body formed by laminating a dielectric layer having a thickness equal to 10 or more times an average particle diameter of a grain included therein and being 3 μm or less; first and second outer electrodes; a first inner electrode having one end forming a first margin together with one end surface of the ceramic body at which the second outer electrode is formed and the other end leading to the first outer electrode; and a second inner electrode having one end forming a second margin together with the other end surface of the ceramic body at which the first outer electrode is formed and the other end leading to the second outer electrode, wherein the first and second margins have different widths under a condition that they are 200 μm or less.
摘要翻译： 提供一种芯片型层叠电容器，其包括：陶瓷体，其通过层叠厚度等于其中包含的晶粒的平均粒径的10倍以上且为3μm以下的电介质层而形成; 第一和第二外部电极; 第一内部电极，其一端与形成有第二外部电极的陶瓷体的一个端面一起形成第一边缘，而另一端通向第一外部电极; 以及第二内部电极，其一端与形成有第一外部电极的陶瓷体的另一个端面一起形成第二边缘，另一端通向第二外部电极，其中第一和第二边缘具有不同的宽度 在200μm以下的条件下。
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公开(公告)号：US20120327557A1
公开(公告)日：2012-12-27
申请号：US13531242
申请日：2012-06-22
申请人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Young Hoon Song , Mi Hee Lee
发明人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Young Hoon Song , Mi Hee Lee
IPC分类号： H01G4/12
摘要： There is provided a chip type laminated capacitor including: a ceramic body formed by laminating a dielectric layer having a thickness equal to 10 or more times an average particle diameter of a grain included therein and being 3 μm or less; first and second outer electrodes; a first inner electrode having one end forming a first margin together with one end surface of the ceramic body at which the second outer electrode is formed and the other end leading to the first outer electrode; and a second inner electrode having one end forming a second margin together with the other end surface of the ceramic body at which the first outer electrode is formed and the other end leading to the second outer electrode, wherein the first and second margins have different widths under a condition that they are 200 μm or less.
摘要翻译： 提供一种芯片型层叠电容器，其包括：陶瓷体，其通过层叠厚度等于其中包含的晶粒的平均粒径的10倍以上且为3μm以下的电介质层而形成; 第一和第二外部电极; 第一内部电极，其一端与形成有第二外部电极的陶瓷体的一个端面一起形成第一边缘，而另一端通向第一外部电极; 以及第二内部电极，其一端与形成有第一外部电极的陶瓷体的另一个端面一起形成第二边缘，另一端通向第二外部电极，其中第一和第二边缘具有不同的宽度 在200μm以下的条件下。
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公开(公告)号：US06914512B2
公开(公告)日：2005-07-05
申请号：US10461334
申请日：2003-06-16
申请人： Dong Seok Park , Nam Chul Kim , Jeong Ho Yoon , Byoung Hwa Lee , Sang Soo Park
发明人： Dong Seok Park , Nam Chul Kim , Jeong Ho Yoon , Byoung Hwa Lee , Sang Soo Park
CPC分类号： H01P5/10
摘要： A 3-line balun transformer includes an unbalanced port for an unbalanced signal, first and second balanced ports for balanced signals, the balanced signals being the same in level and 180 degrees out of phase with each other, a first line having its first end connected to the unbalanced port and its second end connected to ground, a second line arranged in parallel with the first line while being spaced apart from the first line, the second line having its first end and its second end connected to the first balanced port, and a third line arranged in parallel with the second line while being spaced apart from the second, the third line having its first end connected to the first end of the second line and its second end connected to the second balanced port.
摘要翻译： 3线平衡 - 不平衡变压器包括用于不平衡信号的不平衡端口，用于平衡信号的第一和第二平衡端口，平衡信号彼此相同且相位相差180度，其第一端连接 连接到不平衡端口，其第二端连接到地，第二线与第一线平行布置，同时与第一线间隔开，第二线具有其第一端并且其第二端连接到第一平衡端口，以及 第三线与第二线平行布置，同时与第二线隔开，第三线的第一端连接到第二线的第一端，其第二端连接到第二平衡端口。
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公开(公告)号：US06885259B2
公开(公告)日：2005-04-26
申请号：US10623594
申请日：2003-07-22
申请人： Byoung Hwa Lee , Nam Chul Kim , James Mike Peters , Myung Pyo Jun , Jeong Ho Yoon , Ian Lee , Dong Seok Park , Sang Soo Park
发明人： Byoung Hwa Lee , Nam Chul Kim , James Mike Peters , Myung Pyo Jun , Jeong Ho Yoon , Ian Lee , Dong Seok Park , Sang Soo Park
摘要： Disclosed is a matching circuit of a laminated duplexer connected to an antenna terminal while being connected between transmitting and receiving filters to match the transmitting and receiving filters with the antenna terminal, the matching circuit being configured to reduce the physical length of each conductor pattern thereof, thereby being capable of achieving an improved miniaturization thereof. The matching circuit includes a transmitting matching unit constituted by a conductor pattern electrically connected to an antenna electrode connected to the antenna terminal while being electrically connected to the transmitting filter, a first ground electrode vertically spaced apart from the conductor pattern, a receiving matching unit constituted by a conductor pattern electrically connected to the antenna electrode and the receiving filter, and a second ground electrode vertically spaced apart from the conductor pattern of the receiving matching unit. A laminated duplexer provided with the matching circuit is also disclosed. In accordance with the configuration of the matching circuit, it is possible to achieve a reduction in insertion loss, an improvement in the reflection characteristics of an associated antenna, and, thus, an improvement in bandpass characteristics.
摘要翻译： 公开了一种连接到天线端子的层叠双工器的匹配电路，同时连接在发射和接收滤波器之间以将发射和接收滤波器与天线端子匹配，匹配电路被配置为减小其每个导体图案的物理长度， 从而能够实现其小型化。 匹配电路包括发射匹配单元，其由与连接到天线端子的天线电极电连接的导体图案构成，同时电连接到发射滤波器，与导体图案垂直间隔开的第一接地电极，构成的接收匹配单元 通过与天线电极和接收滤波器电连接的导体图案和与接收匹配单元的导体图案垂直间隔开的第二接地电极。 还公开了配备有匹配电路的层压双工器。 根据匹配电路的结构，可以实现插入损耗的降低，相关天线的反射特性的提高，从而提高带通特性。
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公开(公告)号：US06903643B2
公开(公告)日：2005-06-07
申请号：US10462748
申请日：2003-06-17
申请人： Byoung Hwa Lee , Nam Chul Kim , Jeong Ho Yoon , Sang Soo Park , Dong Seok Park
发明人： Byoung Hwa Lee , Nam Chul Kim , Jeong Ho Yoon , Sang Soo Park , Dong Seok Park
CPC分类号： H01F17/0013 , H01F19/04 , H01P5/10
摘要： A balun transformer includes a structure with three .lambda./4 strip lines for converting an unbalanced signal in an unbalanced transmission line into a balanced signal in a balanced transmission line. The balun transformer includes a first dielectric sheet on which a first strip line provided, a second dielectric sheet placed under the first dielectric sheet and on which a second strip line electro-magnetically coupled to the first strip line is provided, a third dielectric sheet placed under the second dielectric sheet and on which a ground pattern is provided, and a fourth dielectric sheet placed under the third dielectric sheet and on which a third strip line is provided. The balun transformer includes the reduced number of strip lines in comparison with the conventional laminated balun transformer, so that the production cost is reduced.
摘要翻译： 平衡不平衡变压器包括具有三个λ/ 4条线的结构，用于将不平衡传输线中的不平衡信号转换成平衡传输线中的平衡信号。 平衡 - 不平衡变压器包括第一电介质片，第一带状线，第二电介质片放置在第一电介质片的下方，第二电介质片设置有电磁耦合到第一带状线的第二带状线， 在第二电介质片材的下方并设有接地图案，以及放置在第三电介质片下方的第四电介质片，并且设有第三带状线。 平衡不平衡转换器与传统的层叠平衡 - 不平衡变压器相比，包括减少数量的带状线，从而降低了生产成本。
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78.发明申请SEMICONDUCTOR INTEGRATED CIRCUIT CHIP, MULTILAYER CHIP CAPACITOR AND SEMICONDUCTOR INTEGRATED CIRCUIT CHIP PACKAGE 有权半导体集成电路芯片，多层芯片电容器和半导体集成电路芯片封装公开(公告)号：US20100117192A1
公开(公告)日：2010-05-13
申请号：US12270457
申请日：2008-11-13
申请人： Byoung Hwa Lee , Min Cheol Park , Ho Cheol Kwak , Haixin Ke , Todd Harvey Hubing
发明人： Byoung Hwa Lee , Min Cheol Park , Ho Cheol Kwak , Haixin Ke , Todd Harvey Hubing
CPC分类号： H01G4/232 , H01G2/06 , H01G4/30 , H01L23/50 , H01L23/642 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2924/19104 , H01L2924/3011
摘要： Disclosed are a semiconductor integrated circuit chip, a multilayer chip capacitor, and a semiconductor integrated circuit chip package. The semiconductor integrated circuit chip includes a semiconductor integrated circuit chip body, an input/output terminal disposed on the outside of the semiconductor integrated circuit chip body, and a decoupling capacitor disposed at a side face of the semiconductor integrated circuit chip body and electrically connected to the input/output terminal. The semiconductor integrated circuit chip cab be obtained, which can maintain an impedance of a power distribution network below a target impedance in a wide frequency range, particularly at a high frequency, by minimizing an inductance between a decoupling capacitor and a semiconductor integrated circuit chip.
摘要翻译： 公开了半导体集成电路芯片，多层片状电容器和半导体集成电路芯片封装。 半导体集成电路芯片包括半导体集成电路芯片体，设置在半导体集成电路芯片体的外部的输入/输出端子和设置在半导体集成电路芯片主体的侧面的去耦电容器，电连接到 输入/输出端子。 可以获得半导体集成电路芯片驾驶室，通过最小化去耦电容器和半导体集成电路芯片之间的电感，可以在较宽的频率范围内，特别是在高频下，将配电网络的阻抗保持在低于目标阻抗的范围内。
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79.发明授权Semiconductor integrated circuit chip, multilayer chip capacitor and semiconductor integrated circuit chip package 有权半导体集成电路芯片，多层片式电容器和半导体集成电路芯片封装公开(公告)号：US08304854B2
公开(公告)日：2012-11-06
申请号：US12270457
申请日：2008-11-13
申请人： Byoung Hwa Lee , Min Cheol Park , Ho Cheol Kwak , Haixin Ke , Todd Harvey Hubing
发明人： Byoung Hwa Lee , Min Cheol Park , Ho Cheol Kwak , Haixin Ke , Todd Harvey Hubing
IPC分类号： H01L29/92
CPC分类号： H01G4/232 , H01G2/06 , H01G4/30 , H01L23/50 , H01L23/642 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2924/19104 , H01L2924/3011
摘要： Disclosed are a semiconductor integrated circuit chip, a multilayer chip capacitor, and a semiconductor integrated circuit chip package. The semiconductor integrated circuit chip includes a semiconductor integrated circuit chip body, an input/output terminal disposed on the outside of the semiconductor integrated circuit chip body, and a decoupling capacitor disposed at a side face of the semiconductor integrated circuit chip body and electrically connected to the input/output terminal. The semiconductor integrated circuit chip cab be obtained, which can maintain an impedance of a power distribution network below a target impedance in a wide frequency range, particularly at a high frequency, by minimizing an inductance between a decoupling capacitor and a semiconductor integrated circuit chip.
摘要翻译： 公开了半导体集成电路芯片，多层片状电容器和半导体集成电路芯片封装。 半导体集成电路芯片包括半导体集成电路芯片体，设置在半导体集成电路芯片体的外部的输入/输出端子和设置在半导体集成电路芯片主体的侧面的去耦电容器，电连接到 输入/输出端子。 可以获得半导体集成电路芯片驾驶室，通过最小化去耦电容器和半导体集成电路芯片之间的电感，可以在较宽的频率范围内，特别是在高频下，将配电网络的阻抗保持在低于目标阻抗的范围内。
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公开(公告)号：US06919748B2
公开(公告)日：2005-07-19
申请号：US10377722
申请日：2003-03-04
申请人： Byoung Hwa Lee , Nam Chul Kim , Jeong Ho Yoon , Sang Soo Park
发明人： Byoung Hwa Lee , Nam Chul Kim , Jeong Ho Yoon , Sang Soo Park
CPC分类号： H01P1/20345
摘要： An dielectric laminated filter improves a skirt characteristic to shift am attenuation pole to a transmitting frequency band while maintaining the same band width of the transmitting frequency band and includes a dielectric block laminated with a plurality of dielectric sheets, ground electrodes formed on front and rear sides of the dielectric block, input and output electrodes formed on both sides of the dielectric body to be separated from the ground electrodes, an inductor pattern having two portions disposed parallel to the resonator patterns coupled to the input and output electrodes and a connecting portion coupling the two portions to induce an inductance coupling with the resonator patterns coupled to the input and output electrodes to improve a filter response characteristic by adjusting the inductance coupling.
摘要翻译： 电介质层压滤波器改善裙边特性，以将衰减极点移动到发射频带，同时保持发射频带的相同带宽，并且包括层叠有多个电介质片的介质块，形成在前侧和后侧的接地电极 介电块的形成在电介体的两侧的输入和输出电极与接地电极分离;电感器图案，具有平行于耦合到输入和输出电极的谐振器图案设置的两个部分，以及连接部分 两部分，以引起与耦合到输入和输出电极的谐振器图案的电感耦合，以通过调节电感耦合来改善滤波器响应特性。
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