-
公开(公告)号：US06885259B2
公开(公告)日：2005-04-26
申请号：US10623594
申请日：2003-07-22
申请人： Byoung Hwa Lee , Nam Chul Kim , James Mike Peters , Myung Pyo Jun , Jeong Ho Yoon , Ian Lee , Dong Seok Park , Sang Soo Park
发明人： Byoung Hwa Lee , Nam Chul Kim , James Mike Peters , Myung Pyo Jun , Jeong Ho Yoon , Ian Lee , Dong Seok Park , Sang Soo Park
摘要： Disclosed is a matching circuit of a laminated duplexer connected to an antenna terminal while being connected between transmitting and receiving filters to match the transmitting and receiving filters with the antenna terminal, the matching circuit being configured to reduce the physical length of each conductor pattern thereof, thereby being capable of achieving an improved miniaturization thereof. The matching circuit includes a transmitting matching unit constituted by a conductor pattern electrically connected to an antenna electrode connected to the antenna terminal while being electrically connected to the transmitting filter, a first ground electrode vertically spaced apart from the conductor pattern, a receiving matching unit constituted by a conductor pattern electrically connected to the antenna electrode and the receiving filter, and a second ground electrode vertically spaced apart from the conductor pattern of the receiving matching unit. A laminated duplexer provided with the matching circuit is also disclosed. In accordance with the configuration of the matching circuit, it is possible to achieve a reduction in insertion loss, an improvement in the reflection characteristics of an associated antenna, and, thus, an improvement in bandpass characteristics.
摘要翻译： 公开了一种连接到天线端子的层叠双工器的匹配电路，同时连接在发射和接收滤波器之间以将发射和接收滤波器与天线端子匹配，匹配电路被配置为减小其每个导体图案的物理长度， 从而能够实现其小型化。 匹配电路包括发射匹配单元，其由与连接到天线端子的天线电极电连接的导体图案构成，同时电连接到发射滤波器，与导体图案垂直间隔开的第一接地电极，构成的接收匹配单元 通过与天线电极和接收滤波器电连接的导体图案和与接收匹配单元的导体图案垂直间隔开的第二接地电极。 还公开了配备有匹配电路的层压双工器。 根据匹配电路的结构，可以实现插入损耗的降低，相关天线的反射特性的提高，从而提高带通特性。
-
公开(公告)号：US06914512B2
公开(公告)日：2005-07-05
申请号：US10461334
申请日：2003-06-16
申请人： Dong Seok Park , Nam Chul Kim , Jeong Ho Yoon , Byoung Hwa Lee , Sang Soo Park
发明人： Dong Seok Park , Nam Chul Kim , Jeong Ho Yoon , Byoung Hwa Lee , Sang Soo Park
CPC分类号： H01P5/10
摘要： A 3-line balun transformer includes an unbalanced port for an unbalanced signal, first and second balanced ports for balanced signals, the balanced signals being the same in level and 180 degrees out of phase with each other, a first line having its first end connected to the unbalanced port and its second end connected to ground, a second line arranged in parallel with the first line while being spaced apart from the first line, the second line having its first end and its second end connected to the first balanced port, and a third line arranged in parallel with the second line while being spaced apart from the second, the third line having its first end connected to the first end of the second line and its second end connected to the second balanced port.
摘要翻译： 3线平衡 - 不平衡变压器包括用于不平衡信号的不平衡端口，用于平衡信号的第一和第二平衡端口，平衡信号彼此相同且相位相差180度，其第一端连接 连接到不平衡端口，其第二端连接到地，第二线与第一线平行布置，同时与第一线间隔开，第二线具有其第一端并且其第二端连接到第一平衡端口，以及 第三线与第二线平行布置，同时与第二线隔开，第三线的第一端连接到第二线的第一端，其第二端连接到第二平衡端口。
-
公开(公告)号：US06903643B2
公开(公告)日：2005-06-07
申请号：US10462748
申请日：2003-06-17
申请人： Byoung Hwa Lee , Nam Chul Kim , Jeong Ho Yoon , Sang Soo Park , Dong Seok Park
发明人： Byoung Hwa Lee , Nam Chul Kim , Jeong Ho Yoon , Sang Soo Park , Dong Seok Park
CPC分类号： H01F17/0013 , H01F19/04 , H01P5/10
摘要： A balun transformer includes a structure with three .lambda./4 strip lines for converting an unbalanced signal in an unbalanced transmission line into a balanced signal in a balanced transmission line. The balun transformer includes a first dielectric sheet on which a first strip line provided, a second dielectric sheet placed under the first dielectric sheet and on which a second strip line electro-magnetically coupled to the first strip line is provided, a third dielectric sheet placed under the second dielectric sheet and on which a ground pattern is provided, and a fourth dielectric sheet placed under the third dielectric sheet and on which a third strip line is provided. The balun transformer includes the reduced number of strip lines in comparison with the conventional laminated balun transformer, so that the production cost is reduced.
摘要翻译： 平衡不平衡变压器包括具有三个λ/ 4条线的结构，用于将不平衡传输线中的不平衡信号转换成平衡传输线中的平衡信号。 平衡 - 不平衡变压器包括第一电介质片，第一带状线，第二电介质片放置在第一电介质片的下方，第二电介质片设置有电磁耦合到第一带状线的第二带状线， 在第二电介质片材的下方并设有接地图案，以及放置在第三电介质片下方的第四电介质片，并且设有第三带状线。 平衡不平衡转换器与传统的层叠平衡 - 不平衡变压器相比，包括减少数量的带状线，从而降低了生产成本。
-
公开(公告)号：US06919748B2
公开(公告)日：2005-07-19
申请号：US10377722
申请日：2003-03-04
申请人： Byoung Hwa Lee , Nam Chul Kim , Jeong Ho Yoon , Sang Soo Park
发明人： Byoung Hwa Lee , Nam Chul Kim , Jeong Ho Yoon , Sang Soo Park
CPC分类号： H01P1/20345
摘要： An dielectric laminated filter improves a skirt characteristic to shift am attenuation pole to a transmitting frequency band while maintaining the same band width of the transmitting frequency band and includes a dielectric block laminated with a plurality of dielectric sheets, ground electrodes formed on front and rear sides of the dielectric block, input and output electrodes formed on both sides of the dielectric body to be separated from the ground electrodes, an inductor pattern having two portions disposed parallel to the resonator patterns coupled to the input and output electrodes and a connecting portion coupling the two portions to induce an inductance coupling with the resonator patterns coupled to the input and output electrodes to improve a filter response characteristic by adjusting the inductance coupling.
摘要翻译： 电介质层压滤波器改善裙边特性，以将衰减极点移动到发射频带，同时保持发射频带的相同带宽，并且包括层叠有多个电介质片的介质块，形成在前侧和后侧的接地电极 介电块的形成在电介体的两侧的输入和输出电极与接地电极分离;电感器图案，具有平行于耦合到输入和输出电极的谐振器图案设置的两个部分，以及连接部分 两部分，以引起与耦合到输入和输出电极的谐振器图案的电感耦合，以通过调节电感耦合来改善滤波器响应特性。
-
公开(公告)号：US08351180B1
公开(公告)日：2013-01-08
申请号：US13531237
申请日：2012-06-22
IPC分类号： H01G4/06
摘要： There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.
摘要翻译： 提供了一种多层陶瓷电容器，包括：多层体，其中多个电介质层在厚度方向上堆叠; 以及形成在所述多层体内并且包括彼此相对设置的第一和第二内部电极的内部电极层; 其中MA1与CA1的比率（MA1 / CA1）在0.07和0.20之间，其中CA1表示在长度和厚度方向上取下的多层体的横截面中的多层体的面积，MA1表示 第一边缘部分是沿着长度和厚度方向截取的第一边缘部分，第一边缘部分是多层体的一部分，除了第一电容形成部分之外，第一和第二内部电极在其中重叠 厚度方向。
-
公开(公告)号：US08315034B2
公开(公告)日：2012-11-20
申请号：US12245856
申请日：2008-10-06
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
摘要： A multilayer chip capacitor includes a capacitor body including a first capacitor part and a second capacitor part, first and second external electrodes respectively formed on first and second longer side faces of the capacitor body, and third and fourth external electrodes respectively formed on first and second shorter side faces of the capacitor body. The first capacitor part includes first and second internal electrodes of opposite polarity, and the second capacitor part includes third and fourth internal electrodes of opposite polarity. The first to fourth internal electrodes each have one lead. The first to fourth external electrodes are respectively connected to the leads of the first to fourth internal electrodes. A series resonance frequency of the first capacitor part is different from that of the second capacitor part. Equivalent series resistance (ESR1) of the first capacitor part and the equivalent series resistance (ESR2) of the second capacitor part satisfy ERS1≧20 mΩ and 0.7(ESR1)≦ESR2≦1.3(ESR1).
摘要翻译： 多层片状电容器包括电容器本体，其包括第一电容器部分和第二电容器部分，分别形成在电容器主体的第一和第二长侧面上的第一和第二外部电极，以及分别形成在第一和第二电极部分上的第三和第四外部电极 电容器主体的较短侧面。 第一电容器部分包括具有相反极性的第一和第二内部电极，并且第二电容器部分包括具有相反极性的第三和第四内部电极。 第一至第四内部电极各有一个引线。 第一至第四外部电极分别连接到第一至第四内部电极的引线。 第一电容器部分的串联谐振频率与第二电容器部分的串联谐振频率不同。 第一电容器部分的等效串联电阻（ESR1）和第二电容器部分的等效串联电阻（ESR2）满足ERS1≥20m＆OHgr; 和0.7（ESR1）＆nlE; ESR2＆N1; 1.3（ESR1）。
-
公开(公告)号：US08184425B2
公开(公告)日：2012-05-22
申请号：US12238796
申请日：2008-09-26
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
CPC分类号： H01G4/228
摘要： There is provided a multilayer capacitor including: a capacitor body where a plurality of dielectric layers are laminated, the capacitor body including first and second surfaces opposing each other in a laminated direction, wherein the first surface provides a mounting surface; a plurality of first and second inner electrodes; an inner connecting conductor; and a plurality of first and second outer electrodes formed on an outer surface of the body, wherein a corresponding one of the outer electrodes having identical polarity to the inner connecting conductor includes at least one outer terminal formed on the first surface of the body to connect to the inner connecting conductor, and at least one outer connecting conductor formed on the second surface of the body to connect a corresponding one of the inner electrodes of identical polarity to the inner connecting conductor.
摘要翻译： 提供了一种层叠电容器，其包括：层叠多个电介质层的电容器体，所述电容器主体包括在层叠方向上彼此相对的第一和第二表面，其中所述第一表面提供安装表面; 多个第一和第二内部电极; 内连接导体; 以及形成在所述主体的外表面上的多个第一外部电极和第二外部电极，其中与所述内部连接导体具有相同极性的相应的外部电极包括形成在所述主体的所述第一表面上的至少一个外部端子，以连接 内部连接导体和形成在主体的第二表面上的至少一个外部连接导体，以将相当极性的相应的一个内部电极与内部连接导体相连接。
-
公开(公告)号：US07817007B2
公开(公告)日：2010-10-19
申请号：US12194935
申请日：2008-08-20
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hyeog Soo Shin , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hyeog Soo Shin , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01F5/00
CPC分类号： H01F17/0013 , H01F3/14 , H01F17/04
摘要： There is provided a laminated inductor including: a body where a plurality of magnetic layers are laminated; a coil part formed on the magnetic layers, the coil part including a plurality of conductor patterns and a plurality of conductive vias; first and second external electrodes formed on an outer surface of the body to connect to both ends of the coil part, respectively; and a non-magnetic conductor formed on at least one of the magnetic layers so as to relax magnetic saturation caused by direct current flowing through the coil part. The laminated inductor employs the non-magnetic conductor as a non-magnetic gap to be simplified in a manufacturing process and effectively improved in DC superposition characteristics.
摘要翻译： 提供一种层叠电感器，包括：层叠有多个磁性层的主体; 形成在所述磁性层上的线圈部分，所述线圈部分包括多个导体图案和多个导电通孔; 第一外部电极和第二外部电极分别形成在主体的外表面上以连接到线圈部分的两端; 以及形成在至少一个磁性层上的非磁性导体，以便缓和由直流电流流过线圈部分的磁饱和。 层叠电感器在制造工艺中使用非磁性导体作为非磁性间隙进行简化，并有效地改善了DC叠加特性。
-
公开(公告)号：US20100254070A1
公开(公告)日：2010-10-07
申请号：US12817046
申请日：2010-06-16
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
摘要： A multilayer chip capacitor includes: a capacitor body having first and second side surfaces and a bottom surface; a plurality of first and second internal electrodes in the capacitor body; first and second external electrodes having a first polarity and formed on the first and second side surfaces, respectively, to cover a respective lower edge of the side surfaces and to partially extend to the bottom surface; and a third external electrode having a second polarity and formed on the bottom surface. The internal electrodes are disposed in perpendicular to the bottom surface. Each of the first internal electrodes has a first lead drawn to the first side and bottom surfaces and a second lead drawn to the second side and bottom surfaces. Each of the second internal electrodes has a third lead drawn to the bottom surface.
摘要翻译： 一种多层片状电容器包括：具有第一和第二侧表面和底表面的电容器本体; 电容器主体中的多个第一和第二内部电极; 第一和第二外部电极分别具有第一极性并形成在第一和第二侧表面上，以覆盖侧表面的相应下边缘并部分地延伸到底面; 和具有第二极性并形成在底面上的第三外部电极。 内部电极垂直于底面设置。 每个第一内部电极具有被引导到第一侧面和底部表面的第一引线和被引导到第二侧面和底部表面的第二引线。 每个第二内部电极具有被引导到底面的第三引线。
-
10.发明授权Multilayer chip capacitor, circuit board apparatus having the capacitor, and circuit board 有权多层片式电容器，具有电容器的电路板装置和电路板公开(公告)号：US07630208B2
公开(公告)日：2009-12-08
申请号：US12198342
申请日：2008-08-26
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H05K1/16
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30 , H01G4/385 , H05K1/0231 , H05K1/113 , H05K2201/09309 , H05K2201/09772 , H05K2201/0979 , H05K2201/10015 , H05K2201/10636 , Y02P70/611
摘要： Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.
摘要翻译： 本发明提供一种多层片状电容器，其包括具有层叠方向配置的第一和第二电容器单元的电容器体; 以及形成在电容器主体外部的多个外部电极。 第一电容器单元包括交替设置在电容器主体的内部的至少一对第一和第二内部电极，第二电容器单元包括交替设置在电容器主体内部的多个第三和第四内部电极， 并且第一至第四内部电极耦合到第一至第四外部电极。 第一电容器单元具有比第二电容器单元更低的等效串联电感（ESL），并且第一电容器单元具有比第二电容器单元更高的等效串联电阻（ESR）。
-
-
-
-
-
-
-
-
-
搜索结果
85 条记录 (耗时 0.048 秒)
