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    Multiple size memories in a programmable logic device
    74.
    发明授权
    Multiple size memories in a programmable logic device 有权
    可编程逻辑器件中的多个大小的存储器

    公开(公告)号：US07236008B1

    公开(公告)日：2007-06-26

    申请号：US11611122

    申请日：2006-12-14

    申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  Andy L. Lee ,  David Lewis

    发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  Andy L. Lee ,  David Lewis

    IPC分类号： G06F7/38 ,  H03K19/177

    CPC分类号： H03K19/1776 ,  H03K19/17728

    摘要： Circuits, methods, and apparatus that provide integrated circuits having memories with multiple sizes. The memories may be dedicated embedded memories, or they may be distributed memories formed using memories or lookup tables in logic elements or other appropriate circuits. Configuration bits not needed by logic elements used for distributed memories can be used for data storage as well. These various memories may be combined or otherwise linked or chained together in different combinations to form larger memories of varying sizes.

    摘要翻译： 提供具有多种尺寸的存储器的集成电路的电路，方法和装置。 存储器可以是专用的嵌入式存储器，或者它们可以是使用逻辑元件或其他适当电路中的存储器或查找表形成的分布式存储器。 用于分布式存储器的逻辑元件不需要的配置位也可以用于数据存储。 这些各种存储器可以以不同的组合组合或以其他方式链接或链接在一起以形成不同大小的较大存储器。

    PCI-compatible programmable logic devices
    76.
    发明授权
    PCI-compatible programmable logic devices 有权
    PCI兼容的可编程逻辑器件

    公开(公告)号：US06271681B1

    公开(公告)日：2001-08-07

    申请号：US09395886

    申请日：1999-09-14

    申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    IPC分类号： H03K19177

    CPC分类号： H03K19/1774 ,  H03K19/17744

    摘要： A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Regions of programmable logic within the device are closely coupled to the data signal output pins and clock signal input pins such that delay between application of a clock signal to the device and output of a data signal from the device is within PCI signal standards for delay. The device also includes output circuitry that can be configured to selectively invert signals to output enable and data input enable terminals of the output circuitry.

    摘要翻译： 可编程逻辑集成电路器件具有几个功能，可帮助其根据PCI特殊兴趣组的外设组件接口（“PCI”）信令协议执行。 器件内的可编程逻辑区域紧密耦合到数据信号输出引脚和时钟信号输入引脚，使得施加时钟信号与器件之间的延迟和来自器件的数据信号的输出之间的延迟处于用于延迟的PCI信号标准之内。 该器件还包括可被配置为选择性地将信号反转到输出电路的输出使能和数据输入使能端的输出电路。

    Logic element for a programmable logic integrated circuit
    77.
    发明授权
    Logic element for a programmable logic integrated circuit 有权
    可编程逻辑集成电路的逻辑元件

    公开(公告)号：US06271680B1

    公开(公告)日：2001-08-07

    申请号：US09606250

    申请日：2000-06-28

    申请人： David W. Mendel ,  Richard G. Cliff

    发明人： David W. Mendel ,  Richard G. Cliff

    IPC分类号： H03K19177

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

    摘要： A logic element (300) for a programmable logic device. The logic element (300) allows two independent logic functions to be carried out during the same clock cycle. A 4-input look-up table (406) is provided using a 3-input look-up table (434) and two 2-input look-up tables. The results of the 4-input lookup table (406) and the 3-input lookup table (434) may be routed simultaneously from the logic element. It also allows a signal to be routed through a logic element (300) while carrying out an independent logic function. Carry logic (425) is provided. The results of the carry logic (486) may be routed to the global and local interconnect structure of the programmable logic device.

    摘要翻译： 一种用于可编程逻辑器件的逻辑元件（300）。 逻辑元件（300）允许在相同的时钟周期内执行两个独立的逻辑功能。 使用3输入查找表（434）和两个2输入查找表来提供4输入查找表（406）。 可以从逻辑元件同时路由4输入查找表（406）和3输入查找表（434）的结果。 它还允许在执行独立的逻辑功能的同时通过逻辑元件（300）路由信号。 提供进位逻辑（425）。 进位逻辑（486）的结果可以被路由到可编程逻辑器件的全局和局部互连结构。

    Programmable logic array integrated circuit devices with interleaved logic array blocks
    78.
    发明授权
    Programmable logic array integrated circuit devices with interleaved logic array blocks 有权
    具有交错逻辑阵列块的可编程逻辑阵列集成电路器件

    公开(公告)号：US06204688B1

    公开(公告)日：2001-03-20

    申请号：US09208124

    申请日：1998-12-09

    申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    IPC分类号： H03K19177

    CPC分类号： H03K19/17736 ,  H03K19/04 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17796

    摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.

    摘要翻译： 可编程逻辑阵列集成电路器件包括以这种区域的交叉行和列的二维阵列布置在器件上的可编程逻辑的多个区域。 每行具有多个相邻的水平导体，并且每列具有多个相邻的垂直导体。 一排中的区域散布有互连相邻区域和相关联的水平和垂直导体的局部导体组。 本地导体也可用于区域内通信，以及相邻区域之间的通信。 辅助信号，例如时钟和区域的清除可以从专用辅助信号导体或正常区域输入中提取。 区域输入信号选择的存储单元要求通过用于共享这些存储单元的各种技术而减少。

    Logic element for a programmable logic integrated circuit
    79.
    发明授权
    Logic element for a programmable logic integrated circuit 失效
    可编程逻辑集成电路的逻辑元件

    公开(公告)号：US6107822A

    公开(公告)日：2000-08-22

    申请号：US102828

    申请日：1998-06-23

    申请人： David W. Mendel ,  Richard G. Cliff

    发明人： David W. Mendel ,  Richard G. Cliff

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

    摘要： A logic element (300) for a programmable logic device. The logic element (300) allows two independent logic functions to be carried out during the same clock cycle. A 4-input look-up table (406) is provided using a 3-input look-up table (434) and two 2-input look-up tables. The results of the 4-input lookup table (406) and the 3-input lookup table (434) may be routed simultaneously from the logic element. It also allows a signal to be routed through a logic element (300) while carrying out an independent logic function. Carry logic (425) is provided. The results of the carry logic (486) may be routed to the global and local interconnect structure of the programmable logic device.

    摘要翻译： 一种用于可编程逻辑器件的逻辑元件（300）。 逻辑元件（300）允许在相同的时钟周期内执行两个独立的逻辑功能。 使用3输入查找表（434）和两个2输入查找表来提供4输入查找表（406）。 可以从逻辑元件同时路由4输入查找表（406）和3输入查找表（434）的结果。 它还允许在执行独立的逻辑功能的同时通过逻辑元件（300）路由信号。 提供进位逻辑（425）。 进位逻辑（486）的结果可以被路由到可编程逻辑器件的全局和局部互连结构。

    Segmented localized conductors for programmable logic devices
    80.
    发明授权
    Segmented localized conductors for programmable logic devices 失效
    用于可编程逻辑器件的分段局部导体

    公开(公告)号：US5963051A

    公开(公告)日：1999-10-05

    申请号：US837117

    申请日：1997-04-14

    申请人： Richard G. Cliff ,  Chiakang Sung

    发明人： Richard G. Cliff ,  Chiakang Sung

    IPC分类号： H03K19/177

    CPC分类号： H03K19/1778 ,  H03K19/17704 ,  H03K19/17796

    摘要： A programmable logic array integrated circuit device having a two-dimensional array of logic array blocks is provided in which the localized conductors serving each logic array block are segmented. The localized conductors are logic array block conductors that convey signals from associated interblock conductors to logic elements in the logic array blocks and local conductors that convey signals between the logic elements. The localized conductor segments are connected to each other by programmable logic connectors.

    摘要翻译： 提供具有逻辑阵列块的二维阵列的可编程逻辑阵列集成电路器件，其中为每个逻辑阵列块服务的局部导体被分段。 局部导体是将信号从相关联的块间导体传送到逻辑阵列块中的逻辑元件和在逻辑元件之间传送信号的局部导体的逻辑阵列块导体。 局部导体段通过可编程逻辑连接器相互连接。