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    High-speed programmable interconnect
    3.
    发明授权
    High-speed programmable interconnect 有权
    高速可编程互连

    公开(公告)号：US06384629B2

    公开(公告)日：2002-05-07

    申请号：US09738403

    申请日：2000-12-15

    申请人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

    发明人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

    IPC分类号： H01L2500

    CPC分类号： H03K19/17736 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17792

    摘要： An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.

    摘要翻译： 水平导体与逻辑元件输入之间的互连改善。 在水平导体和逻辑元件之间的路径中提供信号再生电路，从而隔离和升高信号。 这允许更快的切换操作。 提供路径，允许从水平导体到垂直导体的信号的选择性路由，而不通过逻辑元件。 而且，提供了一种路径，以允许水平导体被路由到多个垂直导体中的任何一个。

    Programming mode selection with JTAG circuits
    5.
    发明授权
    Programming mode selection with JTAG circuits 有权
    使用JTAG电路进行编程模式选择

    公开(公告)号：US06681378B2

    公开(公告)日：2004-01-20

    申请号：US10175980

    申请日：2002-06-19

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    IPC分类号： G06F1750

    CPC分类号： H03K19/1732 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17744 ,  H03K19/17748

    摘要： A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). Specifically, a technique is to reduce the number of dedicated pins used for user I/O, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction stored in an instruction register (220) may be used to replace the programming mode select pins (252) in a programmable logic device (PLD).

    摘要翻译： 通过增加并行传输的数据量来提供更高系统性能的技术是增加可用于输入和输出用户数据（用户I / O）的外部引脚数。 具体来说，一种技术是减少用于用户I / O的专用引脚数，从而为用户I / O提供更多的外部引脚。 用于实现诸如JTAG边界扫描架构的功能的专用引脚也可用于提供其他功能，例如选择编程模式。 在具体实施例中，也可以使用尚未用于存储在指令寄存器（220）中的JTAG边界扫描指令的JTAG指令代码来替代可编程逻辑器件（PLD）中的编程模式选择引脚（252）。

    Programming mode selection with JTAG circuits
    6.
    发明授权
    Programming mode selection with JTAG circuits 失效
    使用JTAG电路进行编程模式选择

    公开(公告)号：US06421812B1

    公开(公告)日：2002-07-16

    申请号：US09094186

    申请日：1998-06-09

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    IPC分类号： G06F1750

    CPC分类号： H03K19/1732 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17744 ,  H03K19/17748

    摘要： A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). Specifically, a technique is to reduce the number of dedicated pins used for user I/O, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction stored in an instruction register (220) may be used to replace the programming mode select pins (252) in a programmable logic device (PLD).

    摘要翻译： 通过增加并行传输的数据量来提供更高系统性能的技术是增加可用于输入和输出用户数据（用户I / O）的外部引脚数。 具体来说，一种技术是减少用于用户I / O的专用引脚数，从而为用户I / O提供更多的外部引脚。 用于实现诸如JTAG边界扫描架构的功能的专用引脚也可用于提供其他功能，例如选择编程模式。 在具体实施例中，也可以使用尚未用于存储在指令寄存器（220）中的JTAG边界扫描指令的JTAG指令代码来替代可编程逻辑器件（PLD）中的编程模式选择引脚（252）。

    PCI-compatible programmable logic devices
    8.
    发明授权
    PCI-compatible programmable logic devices 有权
    PCI兼容的可编程逻辑器件

    公开(公告)号：US06271681B1

    公开(公告)日：2001-08-07

    申请号：US09395886

    申请日：1999-09-14

    申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    IPC分类号： H03K19177

    CPC分类号： H03K19/1774 ,  H03K19/17744

    摘要： A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Regions of programmable logic within the device are closely coupled to the data signal output pins and clock signal input pins such that delay between application of a clock signal to the device and output of a data signal from the device is within PCI signal standards for delay. The device also includes output circuitry that can be configured to selectively invert signals to output enable and data input enable terminals of the output circuitry.

    摘要翻译： 可编程逻辑集成电路器件具有几个功能，可帮助其根据PCI特殊兴趣组的外设组件接口（“PCI”）信令协议执行。 器件内的可编程逻辑区域紧密耦合到数据信号输出引脚和时钟信号输入引脚，使得施加时钟信号与器件之间的延迟和来自器件的数据信号的输出之间的延迟处于用于延迟的PCI信号标准之内。 该器件还包括可被配置为选择性地将信号反转到输出电路的输出使能和数据输入使能端的输出电路。

    Programmable logic array integrated circuit devices with interleaved logic array blocks
    9.
    发明授权
    Programmable logic array integrated circuit devices with interleaved logic array blocks 有权
    具有交错逻辑阵列块的可编程逻辑阵列集成电路器件

    公开(公告)号：US06204688B1

    公开(公告)日：2001-03-20

    申请号：US09208124

    申请日：1998-12-09

    申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    IPC分类号： H03K19177

    CPC分类号： H03K19/17736 ,  H03K19/04 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17796

    摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.

    摘要翻译： 可编程逻辑阵列集成电路器件包括以这种区域的交叉行和列的二维阵列布置在器件上的可编程逻辑的多个区域。 每行具有多个相邻的水平导体，并且每列具有多个相邻的垂直导体。 一排中的区域散布有互连相邻区域和相关联的水平和垂直导体的局部导体组。 本地导体也可用于区域内通信，以及相邻区域之间的通信。 辅助信号，例如时钟和区域的清除可以从专用辅助信号导体或正常区域输入中提取。 区域输入信号选择的存储单元要求通过用于共享这些存储单元的各种技术而减少。