公开(公告)号：US06900502B2

公开(公告)日：2005-05-31

申请号：US10407761

申请日：2003-04-03

申请人： Chung-Hu Ge ,  Chao-Hsuing Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

发明人： Chung-Hu Ge ,  Chao-Hsuing Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

IPC分类号： H01L21/00 ,  H01L21/30 ,  H01L21/762 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/02 ,  H01L29/72 ,  H01L29/772

CPC分类号： H01L21/823807 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7848

摘要： A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.

摘要翻译： 半导体器件10包括其上设置有绝缘层14（例如氧化物如二氧化硅）的衬底12（例如，硅衬底）。 第一半导体材料层16（例如，SiGe）设置在绝缘层14上，并且第二半导体材料层18（例如，Si）设置在第一半导体材料层16上。 第一和第二半导体材料层16和18优选地具有不同的晶格常数，使得第一半导体材料层16是压缩的，并且第二半导体材料层是拉伸18。

公开(公告)号：US20050233552A1

公开(公告)日：2005-10-20

申请号：US11083537

申请日：2005-03-18

申请人： Chung-Hu Ke ,  Chao-Hsiung Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

发明人： Chung-Hu Ke ,  Chao-Hsiung Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

IPC分类号： H01L21/00 ,  H01L21/30 ,  H01L21/762 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/02 ,  H01L29/72 ,  H01L29/772

CPC分类号： H01L21/823807 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7848

摘要： A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.

公开(公告)号：US20050194658A1

公开(公告)日：2005-09-08

申请号：US11114981

申请日：2005-04-26

申请人： Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

发明人： Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/338 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/10 ,  H01L29/74 ,  H01L29/78 ,  H01L31/0328 ,  H01L31/072

CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

摘要： A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at least part of the first trench, and the second trench is at least partially filled with an insulating material.

摘要翻译： 半导体器件包括衬底，第一外延层，第二外延层，第三外延层，第一沟槽和第二沟槽。 第一外延层形成在基板上。 第一层相对于衬底具有晶格失配。 第二外延层形成在第一层上，第二层相对于第一层具有晶格失配。 第三外延层形成在第二层上，第三层相对于第二层具有晶格失配。 因此，第三层可以是应变硅。 第一沟槽延伸穿过第一层。 第二沟槽延伸穿过第三层并且至少部分地穿过第二层。 所述第二沟槽的至少一部分与所述第一沟槽的至少一部分对准，并且所述第二沟槽至少部分地填充有绝缘材料。

公开(公告)号：US20050116360A1

公开(公告)日：2005-06-02

申请号：US10896270

申请日：2004-07-21

申请人： Chien-Chao Huang ,  Fu-Liang Yang ,  Mickey Ken ,  Chenming Hu ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chih-Hsin Ko

发明人： Chien-Chao Huang ,  Fu-Liang Yang ,  Mickey Ken ,  Chenming Hu ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chih-Hsin Ko

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L31/0328

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

摘要： A complementary FET and a method of manufacture is provided. The complementary FET utilizes a substrate having a surface layer with a crystal orientation. Tensile stress, which increases performance of the NMOS FETs, is added by silicided source/drain regions, tensile-stress film, shallow trench isolations, inter-layer dielectric, or the like.

摘要翻译： 提供互补的FET和制造方法。 互补FET使用具有<100>晶体取向的表面层的衬底。 通过硅化源极/漏极区域，拉伸应力膜，浅沟槽隔离层，层间电介质等添加了提高NMOS FET的性能的拉伸应力。

公开(公告)号：US20050093018A1

公开(公告)日：2005-05-05

申请号：US10699574

申请日：2003-10-31

申请人： Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

发明人： Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/338 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/10 ,  H01L29/74 ,  H01L29/78 ,  H01L31/0328 ,  H01L31/072

CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

摘要： A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at least part of the first trench, and the second trench is at least partially filled with an insulating material.

摘要翻译： 半导体器件包括衬底，第一外延层，第二外延层，第三外延层，第一沟槽和第二沟槽。 第一外延层形成在基板上。 第一层相对于衬底具有晶格失配。 第二外延层形成在第一层上，第二层相对于第一层具有晶格失配。 第三外延层形成在第二层上，第三层相对于第二层具有晶格失配。 因此，第三层可以是应变硅。 第一沟槽延伸穿过第一层。 第二沟槽延伸穿过第三层并且至少部分地穿过第二层。 所述第二沟槽的至少一部分与所述第一沟槽的至少一部分对准，并且所述第二沟槽至少部分地填充有绝缘材料。

公开(公告)号：US07875959B2

公开(公告)日：2011-01-25

申请号：US11216512

申请日：2005-08-31

申请人： Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

发明人： Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

摘要： The channel of a MOSFET is selectively stressed by selectively stressing the silicide layers on the gate electrode and the source/drain. Stress in the silicide layer is selectively produced by orienting the larger dimensions of the silicide grains in a first direction and the smaller dimensions in a second, perpendicular direction, with one of the directions being parallel to the direction of carrier movement in the channel and the other direction being perpendicular thereto.

摘要翻译： 通过选择性地施加栅极电极和源极/漏极上的硅化物层来选择性地施加MOSFET的沟道。 硅化物层中的应力选择性地通过使第一方向上的硅化物颗粒的尺寸取向，并且在第二垂直方向上定向较小的尺寸，其中一个方向平行于通道中的载体移动方向，并且 其他方向与其垂直。

公开(公告)号：US20070045849A1

公开(公告)日：2007-03-01

申请号：US11216512

申请日：2005-08-31

申请人： Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

发明人： Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

IPC分类号： H01L23/48

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

摘要： The channel of a MOSFET is selectively stressed by selectively stressing the silicide layers on the gate electrode and the source/drain. Stress in the silicide layer is selectively produced by orienting the larger dimensions of the silicide grains in a first direction and the smaller dimensions in a second, perpendicular direction, with one of the directions being parallel to the direction of carrier movement in the channel and the other direction being perpendicular thereto.

摘要翻译： 通过选择性地施加栅极电极和源极/漏极上的硅化物层来选择性地施加MOSFET的沟道。 硅化物层中的应力选择性地通过使第一方向上的硅化物颗粒的尺寸取向，并且在第二垂直方向上定向较小的尺寸，其中一个方向平行于通道中的载体移动方向，并且 其他方向与其垂直。

公开(公告)号：US07029994B2

公开(公告)日：2006-04-18

申请号：US11083537

申请日：2005-03-18

申请人： Chung-Hu Ge ,  Chao-Hsiung Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

发明人： Chung-Hu Ge ,  Chao-Hsiung Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

IPC分类号： H01L21/20

CPC分类号： H01L21/823807 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7848

摘要： A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.

摘要翻译： 半导体器件10包括其上设置有绝缘层14（例如氧化物如二氧化硅）的衬底12（例如，硅衬底）。 第一半导体材料层16（例如，SiGe）设置在绝缘层14上，并且第二半导体材料层18（例如，Si）设置在第一半导体材料层16上。 第一和第二半导体材料层16和18优选地具有不同的晶格常数，使得第一半导体材料层16是压缩的，并且第二半导体材料层是拉伸18。

公开(公告)号：US20050253166A1

公开(公告)日：2005-11-17

申请号：US10845374

申请日：2004-05-13

申请人： Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

发明人： Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

IPC分类号： H01L21/265 ,  H01L21/324 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L31/072

CPC分类号： H01L29/1054 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/6659 ,  H01L29/7833

摘要： A method is disclosed for forming a semiconductor device using strained silicon. After forming a first substrate material with a first natural lattice constant on a device substrate and a second substrate material with a second natural lattice constant on the first substrate material, a channel, source and drain regions of a field effective transistor are further defined using the first and second substrate materials. After implanting one or more impurity materials to the source and drain regions, and the transistor goes through an annealing process using a high speed heat source other than a Tungsten-Halogen lamp.

摘要翻译： 公开了一种使用应变硅形成半导体器件的方法。 在第一衬底材料上形成具有第一自然晶格常数的第一衬底材料和在第一衬底材料上具有第二自然晶格常数的第二衬底材料之后，使用所述第一衬底材料的场效应晶体管的沟道，源极和漏极区域进一步限定 第一和第二基板材料。 在将一种或多种杂质材料注入到源极和漏极区域之后，并且晶体管经历使用除了钨 - 卤素灯之外的高速热源的退火工艺。

公开(公告)号：US07495267B2

公开(公告)日：2009-02-24

申请号：US11409405

申请日：2006-04-21

申请人： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

发明人： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

IPC分类号： H01L31/0368

CPC分类号： H01L29/78 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76232 ,  H01L29/7846

摘要： A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.

摘要翻译： 包括适用于制造应变通道晶体管的高应变选择性外延顶层的半导体结构。 顶层沉积在一系列一个或多个下层的最上面。 每个层的晶格与其下层的晶格不匹配，其量不小于该系列的最低层与其所在的衬底之间的晶格失配。 沟槽形成在最上层的层中。 沟槽具有圆角，使得填充沟槽的电介质材料符合圆角。 通过在沟槽形成之后加热最上面的串联层来产生圆角。