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    Strained channel on insulator device
    1.
    发明授权
    Strained channel on insulator device 失效
    应变绝缘体上的通道

    公开(公告)号：US07029994B2

    公开(公告)日：2006-04-18

    申请号：US11083537

    申请日：2005-03-18

    申请人： Chung-Hu Ge ,  Chao-Hsiung Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

    发明人： Chung-Hu Ge ,  Chao-Hsiung Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

    IPC分类号： H01L21/20

    CPC分类号： H01L21/823807 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7848

    摘要： A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.

    摘要翻译： 半导体器件10包括其上设置有绝缘层14（例如氧化物如二氧化硅）的衬底12（例如，硅衬底）。 第一半导体材料层16（例如，SiGe）设置在绝缘层14上，并且第二半导体材料层18（例如，Si）设置在第一半导体材料层16上。 第一和第二半导体材料层16和18优选地具有不同的晶格常数，使得第一半导体材料层16是压缩的，并且第二半导体材料层是拉伸18。

    Strained silicon MOS devices
    4.
    发明授权
    Strained silicon MOS devices 有权
    应变硅MOS器件

    公开(公告)号：US07342289B2

    公开(公告)日：2008-03-11

    申请号：US10637351

    申请日：2003-08-08

    申请人： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos H. Diaz ,  Fu-Liang Yang

    发明人： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos H. Diaz ,  Fu-Liang Yang

    IPC分类号： H01L29/76

    CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

    摘要： A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.

    摘要翻译： 一种提高集成电路中MOS器件的载流子迁移率的结构。 该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

    Strained silicon MOS devices
    6.
    发明申请
    Strained silicon MOS devices 有权
    应变硅MOS器件

    公开(公告)号：US20050032321A1

    公开(公告)日：2005-02-10

    申请号：US10637351

    申请日：2003-08-08

    申请人： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos Diaz ,  Fu-Liang Yang

    发明人： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos Diaz ,  Fu-Liang Yang

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78

    CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

    摘要： A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.

    摘要翻译： 一种提高集成电路中MOS器件的载流子迁移率的结构。 该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

    Novel CMOS device
    7.
    发明申请
    Novel CMOS device 审中-公开
    新型CMOS器件

    公开(公告)号：US20060138557A1

    公开(公告)日：2006-06-29

    申请号：US11356865

    申请日：2006-02-17

    申请人： Chien-Chao Huang ,  Chao-Hsing Wang ,  Chung-Hu Ge ,  Chenming Hu

    发明人： Chien-Chao Huang ,  Chao-Hsing Wang ,  Chung-Hu Ge ,  Chenming Hu

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828

    摘要： A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.

    摘要翻译： 一种方法，包括提供具有邻近PMOS器件的NMOS器件的衬底，并在所述NMOS和PMOS器件上形成第一应力层，其中所述第一应力层包括第一拉伸应力层或压缩应力层。 在第一应力层上形成蚀刻停止层，并且从NMOS器件上去除第一应力层和蚀刻停止层的部分，留下PMOS器件上的第一应力层和蚀刻停止层。 第二拉伸应力层形成在NMOS器件上并且在第一应力层和蚀刻停止层上方，并且第二拉伸应力层和蚀刻停止层的部分从PMOS器件上除去，留下第二拉伸 在NMOS器件上的应力层。

    CMOS device
    8.
    发明授权
    CMOS device 有权
    CMOS器件

    公开(公告)号：US07022561B2

    公开(公告)日：2006-04-04

    申请号：US10307619

    申请日：2002-12-02

    申请人： Chien-Chao Huang ,  Chao-Hsing Wang ,  Chung-Hu Ge ,  Chenming Hu

    发明人： Chien-Chao Huang ,  Chao-Hsing Wang ,  Chung-Hu Ge ,  Chenming Hu

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828

    摘要： A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.

    摘要翻译： 一种方法，包括提供具有邻近PMOS器件的NMOS器件的衬底，并在所述NMOS和PMOS器件上形成第一应力层，其中所述第一应力层包括第一拉伸应力层或压缩应力层。 在第一应力层上形成蚀刻停止层，并且从NMOS器件上去除第一应力层和蚀刻停止层的部分，留下PMOS器件上的第一应力层和蚀刻停止层。 第二拉伸应力层形成在NMOS器件上并且在第一应力层和蚀刻停止层上方，并且第二拉伸应力层和蚀刻停止层的部分从PMOS器件上除去，留下第二拉伸 在NMOS器件上的应力层。