公开(公告)号：US07301170B2

公开(公告)日：2007-11-27

申请号：US11180989

申请日：2005-07-12

申请人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

发明人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

IPC分类号： H01L29/04

CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/3276 ,  Y10S438/924

摘要： The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.

摘要翻译： 本发明提供一种TFT阵列面板及其制造方法，其特征在于，具有含有Al的金属的下层和包含钼（Mo）的钼合金（Mo合金）的上层的信号线，至少包括 铌（Nb），钒（V）和钛（Ti）之一。 因此，防止在蚀刻工艺中可能出现的底切，突出和小鼠咬合，并且提供具有低电阻率和良好接触特性的信号线的TFT阵列面板。

公开(公告)号：US20070102770A1

公开(公告)日：2007-05-10

申请号：US11619451

申请日：2007-01-03

申请人： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

发明人： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

IPC分类号： H01L29/76

CPC分类号： H01L27/1288 ,  G02F2001/136236 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733

摘要： A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极 在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层 露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

公开(公告)号：US20060091396A1

公开(公告)日：2006-05-04

申请号：US11249500

申请日：2005-10-14

申请人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L29/04

CPC分类号： H01L27/3279 ,  H01L27/124 ,  H01L27/1288 ,  H01L51/0023 ,  H01L51/56

摘要： The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.

摘要翻译： 本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

公开(公告)号：US20060076562A1

公开(公告)日：2006-04-13

申请号：US11215067

申请日：2005-08-29

申请人： Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

发明人： Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

IPC分类号： H01L29/04 ,  H01L27/148

CPC分类号： H01L27/124 ,  H01L27/1288 ,  H01L29/12 ,  H01L29/458

摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode at on the gate electrode; and a pixel electrode electrically connected to the drain electrode.

摘要翻译： 本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在栅极绝缘层上并与栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地与扩散阻挡层接触并且与栅电极上的源电极相对; 以及电连接到漏电极的像素电极。

公开(公告)号：US20050221546A1

公开(公告)日：2005-10-06

申请号：US11082967

申请日：2005-03-18

申请人： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

发明人： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

IPC分类号： G02F1/1368 ,  G09F9/30 ,  G09G3/36 ,  G09G3/38 ,  H01L21/00 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L27/1288 ,  G02F2001/136236 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733

摘要： A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极 在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层 露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

公开(公告)号：US08551307B2

公开(公告)日：2013-10-08

申请号：US12779459

申请日：2010-05-13

申请人： Do-Hyun Kim ,  Dong-Hoon Lee ,  Chang-Oh Jeong

发明人： Do-Hyun Kim ,  Dong-Hoon Lee ,  Chang-Oh Jeong

IPC分类号： C23C14/34

CPC分类号： C23C14/3407 ,  C23C14/3464 ,  H01J37/342 ,  H01J37/3435

摘要： A sputtering target apparatus is provided. The sputtering target apparatus includes a first target assembly including a first target array having a first target, a second target disposed adjacent to the first target, and a first target dividing region disposed between the first and second targets, the first target assembly extending along a first direction, wherein the first target dividing region has a longitudinal cross-section that is oblique with respect to the first direction.

摘要翻译： 提供溅射靶设备。 溅射靶设备包括：第一目标组件，其包括具有第一靶的第一靶阵列，与第一靶相邻设置的第二靶;以及设置在第一靶和第二靶之间的第一靶分离区， 第一方向，其中第一目标分割区域具有相对于第一方向倾斜的纵向横截面。

公开(公告)号：US20110114940A1

公开(公告)日：2011-05-19

申请号：US12818047

申请日：2010-06-17

申请人： Do-Hyun Kim ,  Kyoung-Jae Chung ,  Seung-Ha Choi ,  Dong-Hoon Lee ,  Chang-Oh Jeong ,  Suk-Won Jung

发明人： Do-Hyun Kim ,  Kyoung-Jae Chung ,  Seung-Ha Choi ,  Dong-Hoon Lee ,  Chang-Oh Jeong ,  Suk-Won Jung

IPC分类号： H01L29/786 ,  H01L21/36

CPC分类号： H01L27/1225 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02664 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262

摘要： A thin film transistor array panel includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a gate insulating layer disposed on the gate line; an semiconductive oxide layer disposed on the gate insulating layer; a data line disposed on the semiconductive oxide layer and including a source electrode; a drain electrode facing the source electrode on the semiconductive oxide layer; and a passivation layer disposed on the data line. The semiconductive oxide layer is patterned with chlorine (Cl) containing gas which alters relative atomic concentrations of primary semiconductive characteristic-providing elements of the semiconductive oxide layer at least at a portion where a transistor channel region is defined.

摘要翻译： 薄膜晶体管阵列面板包括：基板; 栅极线，设置在所述基板上并且包括栅电极; 设置在栅极线上的栅极绝缘层; 设置在所述栅极绝缘层上的半导体氧化物层; 数据线，设置在所述半导体氧化物层上并包括源电极; 在半导体氧化物层上面对源电极的漏电极; 以及设置在数据线上的钝化层。 至少在限定了晶体管沟道区域的部分，半导体氧化物层用含氯（Cl）的气体构图，该气体改变半导体氧化物层的初级半导体特性提供元件的相对原子浓度。

公开(公告)号：US20110068340A1

公开(公告)日：2011-03-24

申请号：US12652379

申请日：2010-01-05

申请人： Dong-Hoon Lee ,  Do-Hyun Kim ,  Chang-Oh Jeong ,  O-Sung Seo ,  Xin-Xing Li

发明人： Dong-Hoon Lee ,  Do-Hyun Kim ,  Chang-Oh Jeong ,  O-Sung Seo ,  Xin-Xing Li

IPC分类号： H01L33/00 ,  H01L21/336

CPC分类号： H01L27/124 ,  H01L29/78618

摘要： A thin film transistor array panel includes an insulating substrate. A gate line is formed on the insulating substrate and has a gate electrode. A gate insulating layer is formed on the gate line. A semiconductor layer is formed on the gate insulating layer and overlaps the gate electrode. Diffusion barriers are formed on the semiconductor layer and contain nitrogen. A data line crosses the gate line and has a source electrode partially contacting the diffusion barriers and a drain electrode partially contacting the diffusion barriers and facing the source electrode. The drain electrode is on the gate electrode. A pixel electrode is electrically connected to the drain electrode.

摘要翻译： 薄膜晶体管阵列面板包括绝缘基板。 在绝缘基板上形成栅极线，并具有栅电极。 在栅极线上形成栅极绝缘层。 半导体层形成在栅极绝缘层上并与栅电极重叠。 在半导体层上形成扩散阻挡层并含有氮。 数据线与栅极线交叉，并且具有部分地接触扩散阻挡层的源电极和部分地接触扩散阻挡层并面向源电极的漏电极。 漏电极在栅电极上。 像素电极电连接到漏电极。

公开(公告)号：US08470623B2

公开(公告)日：2013-06-25

申请号：US12818047

申请日：2010-06-17

申请人： Do-Hyun Kim ,  Kyoung-Jae Chung ,  Seung-Ha Choi ,  Dong-Hoon Lee ,  Chang-Oh Jeong ,  Suk-Won Jung

发明人： Do-Hyun Kim ,  Kyoung-Jae Chung ,  Seung-Ha Choi ,  Dong-Hoon Lee ,  Chang-Oh Jeong ,  Suk-Won Jung

IPC分类号： H01L21/00

CPC分类号： H01L27/1225 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02664 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262

摘要： A thin film transistor array panel includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a gate insulating layer disposed on the gate line; an semiconductive oxide layer disposed on the gate insulating layer; a data line disposed on the semiconductive oxide layer and including a source electrode; a drain electrode facing the source electrode on the semiconductive oxide layer; and a passivation layer disposed on the data line. The semiconductive oxide layer is patterned with chlorine (Cl) containing gas which alters relative atomic concentrations of primary semiconductive characteristic-providing elements of the semiconductive oxide layer at least at a portion where a transistor channel region is defined.

摘要翻译： 薄膜晶体管阵列面板包括：基板; 栅极线，设置在所述基板上并且包括栅电极; 设置在栅极线上的栅极绝缘层; 设置在所述栅极绝缘层上的半导体氧化物层; 数据线，设置在所述半导体氧化物层上并包括源电极; 在半导体氧化物层上面对源电极的漏电极; 以及设置在数据线上的钝化层。 至少在限定了晶体管沟道区域的部分，半导体氧化物层用含氯（Cl）的气体构图，该气体改变半导体氧化物层的初级半导体特性提供元件的相对原子浓度。

公开(公告)号：US08035110B2

公开(公告)日：2011-10-11

申请号：US12498816

申请日：2009-07-07

申请人： Do-Hyun Kim ,  Pil-Sang Yun ,  Ki-Won Kim ,  Dong-Hoon Lee ,  Chang-Oh Jeong

发明人： Do-Hyun Kim ,  Pil-Sang Yun ,  Ki-Won Kim ,  Dong-Hoon Lee ,  Chang-Oh Jeong

IPC分类号： H01L29/04

CPC分类号： H01L29/7869 ,  H01L27/12 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78618

摘要： A thin-film transistor (TFT) substrate has improved electrical properties and reduced appearance defects and a method of fabricating the TFT substrate, are provided. The TFT substrate includes: gate wiring which is formed on a surface of an insulating substrate; oxide active layer patterns which are formed on the gate wiring and include an oxide of a first material; buffer layer patterns which are disposed on the oxide active layer patterns to directly contact the oxide active layer patterns and include a second material; and data wiring which is formed on the buffer layer patterns to insulatedly cross the gate wiring, wherein a Gibbs free energy of the oxide of the first material is lower than a Gibbs free energy of an oxide of the second material.

摘要翻译： 薄膜晶体管（TFT）基板具有改善的电性能和减少的外观缺陷以及制造TFT基板的方法。 TFT基板包括：形成在绝缘基板的表面上的栅极布线; 氧化物活性层图案，其形成在栅极布线上并且包括第一材料的氧化物; 缓冲层图案，其设置在所述氧化物活性层图案上以直接接触所述氧化物活性层图案并且包括第二材料; 以及形成在所述缓冲层图案上以绝缘地穿过所述栅极布线的数据布线，其中所述第一材料的氧化物的吉布斯自由能低于所述第二材料的氧化物的吉布斯自由能。