公开(公告)号：US10658576B2

公开(公告)日：2020-05-19

申请号：US16580025

申请日：2019-09-24

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Kerry Joseph Nagel ,  Chaitanya Mudivarthi ,  Sanjeev Aggarwal

IPC: H01L43/12 ,  H01L43/08

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

公开(公告)号：US10600460B2

公开(公告)日：2020-03-24

申请号：US16157315

申请日：2018-10-11

Applicant: Everspin Technologies, Inc.

Inventor： Sarin Deshpande ,  Sanjeev Aggarwal ,  Jason Janesky ,  Jon Slaughter ,  Phillip Lopresti

IPC: G11C11/16 ,  H01F10/32 ,  H01L27/22 ,  H01L43/02

Abstract: Spin-orbit-torque (SOT) control strip lines are provided along the sides of free layers in perpendicular magnetic tunnel junction devices. Current flowing through such SOT control strip lines injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used to force the magnetic state of the free layer to a particular state based on the direction of the current through the SOT control strip line. In other embodiments, the SOT provides an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction. Some embodiments have dedicated strip lines for a single magnetic tunnel junction such that a three-terminal device results. Other embodiments have multiple magnetic tunnel junctions sharing a strip line, where the strip line can be used to reset all of the magnetic tunnel junctions to the same state and can also be used as an assist such that individual magnetic tunnel junctions can be written using selection circuitry.

公开(公告)号：US20180145248A1

公开(公告)日：2018-05-24

申请号：US15855984

申请日：2017-12-27

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Sanjeev Aggarwal ,  Kerry Joseph Nagel

IPC: H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11B5/84 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.

公开(公告)号：US09893275B2

公开(公告)日：2018-02-13

申请号：US15396700

申请日：2017-01-02

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev Aggarwal ,  Kerry Nagel ,  Jason Janesky

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.

公开(公告)号：US20180033959A1

公开(公告)日：2018-02-01

申请号：US15727905

申请日：2017-10-09

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Kerry Joseph Nagel ,  Chaitanya Mudivarthi ,  Sanjeev Aggarwal

IPC: H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

公开(公告)号：US09728583B2

公开(公告)日：2017-08-08

申请号：US15249559

申请日：2016-08-29

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Sanjeev Aggarwal ,  Moazzem Hossain ,  Nicholas Rizzo

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack.

公开(公告)号：US09722176B2

公开(公告)日：2017-08-01

申请号：US14991660

申请日：2016-01-08

Applicant: Everspin Technologies, Inc.

Inventor： Chaitanya Mudivarthi ,  Sarin A. Deshpande ,  Sanjeev Aggarwal

IPC: H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  G11B5/31 ,  H01L43/02

CPC classification number: H01L43/12 ,  G11B5/3163 ,  G11C11/161 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  Y10T29/49021

Abstract: Methods for manufacturing magnetoresistive devices are presented in which isolation of magnetic layers in the magnetoresistive stack is achieved by oxidizing exposed sidewalls of the magnetic layers prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls.

公开(公告)号：US09711566B1

公开(公告)日：2017-07-18

申请号：US15230402

申请日：2016-08-06

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Sanjeev Aggarwal ,  Kerry Joseph Nagel ,  Sarin A. Deshpande

IPC: H01L29/82 ,  H01L43/00 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

公开(公告)号：US09698341B2

公开(公告)日：2017-07-04

申请号：US15081397

申请日：2016-03-25

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Sanjeev Aggarwal

IPC: H01L43/12 ,  H01L43/08 ,  G11B5/84 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  G11B5/84 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using a plurality of masks. The magnetoresistive-based device includes magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer. In one embodiment, the method may include removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first mask, to form a first electrode and a first magnetic materials, respectively, and removing the tunnel barrier layer and the second magnetic materials layer unprotected by a second mask to form a tunnel barrier and second magnetic materials, and the second electrically conductive layer unprotected by the second mask to form, and a second electrode.

公开(公告)号：US09343661B2

公开(公告)日：2016-05-17

申请号：US14296189

申请日：2014-06-04

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Kerry Joseph Nagel ,  Sanjeev Aggarwal ,  Chaitanya Mudivarthi

IPC: H01L43/12 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.

Abstract translation: 在形成用于磁阻器件的顶部电极时，使用非反应性剥离工艺剥离用于图案化电极的光致抗蚀剂。 这种非反应性汽提方法使用水蒸汽或一些其它非氧化气体，其也钝化了磁阻装置的暴露部分。 在这种磁阻器件中，包括非反应性间隔层，其有助于防止磁阻器件中的层之间的扩散，其中间隔层的非反应性质防止可能干扰磁阻的下部的精确形成的侧壁粗糙度 设备。