公开(公告)号：US11508810B2

公开(公告)日：2022-11-22

申请号：US17097425

申请日：2020-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jagar Singh ,  Shiv Kumar Mishra

IPC: H01L29/06 ,  H01L29/872 ,  H01L27/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.

公开(公告)号：US10699961B2

公开(公告)日：2020-06-30

申请号：US16030243

申请日：2018-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Edward J. Nowak

IPC: H01L21/8234 ,  H01L29/10 ,  H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L21/265 ,  H01L21/266 ,  H01L21/02 ,  H01L21/3105

Abstract: Structures for switches and methods for forming structures that include a switch. A first well and a section well are arranged in a substrate. Trench isolation regions are arranged in the substrate to define multiple active device regions. Each of the active device regions includes a section of the first well that is surrounded by the trench isolation regions. The second well has an opposite conductivity type from the first well. The active device regions and the trench isolation regions are arranged between the top surface of the substrate and the second well, and the second well is contiguous with the trench isolation regions.

公开(公告)号：US20200144404A1

公开(公告)日：2020-05-07

申请号：US16177877

申请日：2018-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joshua Dillon ,  Siva P. Adusumilli ,  Jagar Singh ,  Anthony Stamper ,  Laura Schutz

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/872

Abstract: One device disclosed herein includes, among other things, first and second conductive features embedded in a first dielectric layer, a cap layer positioned above the first dielectric layer, a ballistic transport material contacting the first conductive member and positioned above a portion of the first dielectric layer, and first and second contacts contacting the first and second conductive features.

公开(公告)号：US20190326413A1

公开(公告)日：2019-10-24

申请号：US15960965

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Arkadiusz Malinowski ,  Jagar Singh

IPC: H01L29/66 ,  H01L29/08

Abstract: Methods, apparatus, and systems for forming a semiconductor substrate comprising a well region containing a first impurity; forming a gate on the semiconductor substrate above the well region; implanting a second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first concentration; removing an upper portion of each second impurity region, to yield two source/drain (S/D) cavities above two depletion regions; and growing epitaxially a doped S/D region in each S/D cavity, wherein each S/D region comprises the second impurity having a second concentration greater than the first concentration.

公开(公告)号：US10453605B2

公开(公告)日：2019-10-22

申请号：US15729992

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Jagar Singh

IPC: H01F5/00 ,  H01F41/063 ,  H01F41/12 ,  H01F5/06 ,  H01F41/34 ,  H01F17/00 ,  H01F41/04 ,  H01L21/00 ,  H01L49/02

Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.

公开(公告)号：US20190131406A1

公开(公告)日：2019-05-02

申请号：US15797606

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Jagar Singh ,  Hui Zang

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed that extend vertically from a top surface of a substrate. A body region is arranged partially in the substrate and partially in the first fin. A drain region is arranged partially in the substrate, partially in the first fin, and partially in the second fin. The body and drain regions respectively have opposite first and second conductivity types. A source region of the second conductivity type is located within the first well in the first fin, and a gate structure is arranged to overlap with a portion of the first fin. The first fin is separated from the second fin by a cut extending vertically to the top surface of the substrate. An isolation region is arranged in the cut between the first fin and the second fin.

公开(公告)号：US10236367B2

公开(公告)日：2019-03-19

申请号：US15642732

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Shiv Kumar Mishra

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/737 ,  H01L29/10 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/266

Abstract: A device includes a substrate, a first well doped with dopants of a first conductivity type defined in the substrate, and a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the substrate adjacent the first well to define a PN junction. The second well includes a silicon alloy portion displaced from the PN junction. A collector region contacts one of the first or second wells and has a dopant concentration higher than its contacted well. An emitter region contacts the other of the first or second wells and is doped with dopants of the first or second conductivity type different than the first or second well contacted by the emitter region. A base region contacts the other of the first or second well and has a dopant concentration higher than the first or second well contacted by the base region.

公开(公告)号：US20190013402A1

公开(公告)日：2019-01-10

申请号：US15642675

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Shiv Kumar Mishra

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a first well doped with dopants of a first conductivity type defined in the substrate, and a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the substrate adjacent the first well to define a PN junction between the first and second wells. The second well includes a silicon alloy portion displaced from the PN junction. A source region is positioned in one of the first well or the second well. A drain region is positioned in the other of the first well or the second well. A gate structure is positioned above the substrate laterally positioned between the source region and the drain region.

公开(公告)号：US09966459B2

公开(公告)日：2018-05-08

申请号：US14476976

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Biswanath Senapati ,  Jagar Singh

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L27/06 ,  G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01L29/417 ,  H01L29/423 ,  H01L27/02

CPC classification number: H01L29/735 ,  G01R31/2621 ,  G01R31/2884 ,  H01L22/34 ,  H01L27/0259 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/42304

Abstract: A symmetrical lateral bipolar junction transistor (SLBJT) is provided. The SLBJT includes a p-type semiconductor substrate, a n-type well, an emitter of a SLBJT situated in the n-type well, a base of the SLBJT situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the SLBJT situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well. The SLBJT is used to characterize a transistor in a circuit by electrically coupling the SLBJT to a gate of the test transistor, applying a voltage to the gate, and characterizing aspect(s) of the test transistor under the applied voltage. The SLBJT protects the gate against damage to the gate dielectric.

公开(公告)号：US09905668B2

公开(公告)日：2018-02-27

申请号：US15057791

申请日：2016-03-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/45 ,  H01L29/40 ,  H01L29/735 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/66325 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/402 ,  H01L29/41708 ,  H01L29/45 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7393

Abstract: A structure, including a bipolar junction transistor and method of fabrication thereof, is provided herein. The bipolar junction transistor includes: a substrate including a substrate region having a first conductivity type; an emitter region over a first portion of the substrate region, the emitter region having a second conductivity type; a collector region over a second portion of the substrate region, the collector region having the second conductivity type; and, a base region overlie structure disposed over, in part, the substrate region. The base region overlie structure separates the emitter region from the collector region and aligns to a base region of the bipolar junction transistor within the substrate region, between the first portion and the second portion of the substrate region.