公开(公告)号：US20190181250A1

公开(公告)日：2019-06-13

申请号：US16278268

申请日：2019-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik ,  Alvin J. Joseph ,  Peter B. Gray

IPC: H01L29/732 ,  H01L29/08 ,  H01L21/762 ,  H01L29/417 ,  H01L29/73 ,  H01L29/10 ,  H01L29/06

Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.

公开(公告)号：US20190081597A1

公开(公告)日：2019-03-14

申请号：US15701672

申请日：2017-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Alvin J. Joseph ,  John J. Pekarik

IPC: H03F1/22 ,  H01L27/07 ,  H01L27/06 ,  H01L27/12 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06

Abstract: Structures for a cascode integrated circuit and methods of forming such structures. A field-effect transistor of the structure includes a gate electrode finger, a first source/drain region, and a second source/drain region. A bipolar junction transistor of the structure includes a first terminal, a base layer with an intrinsic base portion arranged on the first terminal, and a second terminal that includes one or more fingers arranged on the intrinsic base portion of the base layer. The intrinsic base portion of the base layer is arranged in a vertical direction between the first terminal and the second terminal. The first source/drain region is coupled with the first terminal, and the first source/drain region at least partially surrounds the bipolar junction transistor.

公开(公告)号：US10164101B1

公开(公告)日：2018-12-25

申请号：US15790707

申请日：2017-10-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata A. Camillo-Castillo ,  Anthony K. Stamper ,  Vibhor Jain ,  Mark D. Jaffe

IPC: H01L21/82 ,  H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L21/764 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with improved channel mobility and methods of manufacture. A structure includes: a curved beam structure formed from at least one stressed material; a cavity below the curved beam structure; and at least one semiconductor device on a top portion or a bottom portion of the curved beam structure whose carrier mobility is increased or decreased by a curvature of the curved beam structure.

公开(公告)号：US20180226292A1

公开(公告)日：2018-08-09

申请号：US15425384

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain

IPC: H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76289 ,  H01L21/6835 ,  H01L21/76283 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/7317 ,  H01L29/7371 ,  H01L29/78 ,  H01L2221/68345

Abstract: Structures with trench isolation and methods for making a structure with trench isolation. A transistor is formed by front-end-of-line processing on a first surface of a semiconductor substrate. A barrier layer is formed by middle-of-line processing on the transistor and the first surface of the semiconductor substrate. After the transistor and the barrier layer are formed, a trench is etched into the semiconductor substrate from a second surface of the semiconductor substrate that is opposite from the first surface of the semiconductor substrate. The trench, which is used to form an isolation region, may terminate on a dielectric layer associated with the transistor or may terminate on the barrier layer.

公开(公告)号：US20180175180A1

公开(公告)日：2018-06-21

申请号：US15383171

申请日：2016-12-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu ,  David L. Harame ,  Renata Camillo-Castillo

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/417 ,  H01L21/265 ,  H01L29/735 ,  H01L27/12

CPC classification number: H01L29/737 ,  H01L21/26513 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/735

Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.

公开(公告)号：US09653566B2

公开(公告)日：2017-05-16

申请号：US14958345

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES Inc

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater ,  Anthony K. Stamper

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/66242 ,  H01L29/0649 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer.

公开(公告)号：US20170098699A1

公开(公告)日：2017-04-06

申请号：US14874039

申请日：2015-10-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Qizhi Liu ,  Vibhor Jain ,  James W. Adkisson ,  David L. Harame

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/04 ,  H01L21/762 ,  H01L21/225

CPC classification number: H01L29/732 ,  H01L21/76 ,  H01L21/762 ,  H01L29/0642 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7371

Abstract: Device structure and fabrication methods for a bipolar junction transistor. One or more trench isolation regions are formed in a substrate to define a device region having a first width. A protect layer is formed on a top surface of the one or more trench isolation regions and a top surface of the device region. An opening is formed in the protect layer. The opening is coincides with the top surface of the first device region and has a second width that is less than or equal to the first width of the first device region. A base layer is formed that has a first section on the device region inside the first opening and a second section on the protect layer.

公开(公告)号：US09543403B2

公开(公告)日：2017-01-10

申请号：US14601655

申请日：2015-01-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Qizhi Liu

IPC: H01L29/00 ,  H01L29/66 ,  H01L21/306 ,  H01L29/73 ,  H01L29/08

CPC classification number: H01L29/66234 ,  H01L21/306 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/0826 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7371

Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed on the first semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the substrate are etched to define first and second emitter fingers from the second semiconductor layer and trenches in the substrate that are laterally positioned between the first and second emitter fingers. The first semiconductor layer may function as a base layer in the device structure.

Abstract translation: 用于双极结晶体管的器件结构以及制造用于双极结型晶体管的器件结构的方法。 在基板上形成第一半导体层，在第一半导体层上形成第二半导体层。 蚀刻第一半导体层，第二半导体层和衬底以限定来自第二半导体层的第一和第二发射极指状物以及横向位于第一和第二发射极指之间的衬底中的沟槽。 第一半导体层可以用作器件结构中的基层。

公开(公告)号：US09496377B2

公开(公告)日：2016-11-15

申请号：US14747525

申请日：2015-06-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Peng Cheng ,  Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/732 ,  H01L29/73 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/7371

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer. A trench is formed that penetrates through the extrinsic base layer to the etch stop layer. The trench is formed by etching the extrinsic base layer selective to the etch stop layer. The first trench is extended through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer. After the trench is extended through the etch stop layer, an emitter is formed using the trench.

公开(公告)号：US09496250B2

公开(公告)日：2016-11-15

申请号：US14563097

申请日：2014-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: G06F17/50 ,  H01L27/02 ,  H01L29/735 ,  H01L21/762 ,  H01L29/73 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/732

CPC classification number: H01L27/0207 ,  G06F17/5063 ,  G06F17/5072 ,  H01L21/76224 ,  H01L27/082 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/7371

Abstract: Methods for designing and fabricating a bipolar junction transistor. A predetermined size for a device region of the bipolar junction transistor is determined based on a given current gain. A trench isolation layout is determined for a plurality of trench isolation regions to be formed in a substrate to surround the device region. The trench isolation regions are laterally spaced relative to each other in the trench isolation layout in order to set the predetermined size of the device region. An interconnect layout is determined that specifies one or more contacts coupled with a terminal of the bipolar junction transistor. The specification of the one or more contacts in the interconnect layout is unchanged by the determination of the trench isolation layout.

Abstract translation: 双极结型晶体管的设计和制造方法。 基于给定的电流增益确定双极结晶体管的器件区域的预定尺寸。 确定要在衬底中形成以包围器件区域的多个沟槽隔离区域的沟槽隔离布局。 沟槽隔离区域在沟槽隔离布置中相对于彼此横向隔开，以便设定器件区域的预定尺寸。 确定互连布局，其指定与双极结型晶体管的端子耦合的一个或多个触点。 通过确定沟槽隔离布局，互连布局中的一个或多个触点的规格不变。