公开(公告)号：US10164101B1

公开(公告)日：2018-12-25

申请号：US15790707

申请日：2017-10-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata A. Camillo-Castillo ,  Anthony K. Stamper ,  Vibhor Jain ,  Mark D. Jaffe

IPC: H01L21/82 ,  H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L21/764 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with improved channel mobility and methods of manufacture. A structure includes: a curved beam structure formed from at least one stressed material; a cavity below the curved beam structure; and at least one semiconductor device on a top portion or a bottom portion of the curved beam structure whose carrier mobility is increased or decreased by a curvature of the curved beam structure.

公开(公告)号：US09761525B1

公开(公告)日：2017-09-12

申请号：US15142525

申请日：2016-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Terence B. Hook ,  Richard A. Phelps ,  Anthony K. Stamper ,  Renata A. Camillo-Castillo

IPC: H01L29/76 ,  H01L29/94 ,  H01L23/528 ,  H01L29/06 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L23/5283 ,  H01L21/6835 ,  H01L23/485 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L29/0649 ,  H01L29/1087 ,  H01L29/404 ,  H01L29/7831 ,  H01L29/7832 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple back gate transistor structures and methods of manufacture. The structure includes: a transistor formed over a semiconductor material and an underlying substrate; and multiple isolated contact regions under a body or channel of the transistor, structured to provide a local potential to the body of the transistor at different locations.

公开(公告)号：US10153361B2

公开(公告)日：2018-12-11

申请号：US15360295

申请日：2016-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata A. Camillo-Castillo ,  Vibhor Jain ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L29/737 ,  H01L21/8222 ,  H01L21/02 ,  H01L21/268 ,  H01L21/324 ,  H01L27/082 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66 ,  H03F3/21

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor device integration schemes on a same wafer and methods of manufacture. The structure includes: a power amplifier (PA) device comprising a base, a collector and an emitter on a wafer; and a low-noise amplifier (LNA) device comprising a base, a collector and an emitter on the wafer, with the emitter having a same crystalline structure as the base.

公开(公告)号：US10211090B2

公开(公告)日：2019-02-19

申请号：US15291561

申请日：2016-10-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L29/732 ,  H01L29/737 ,  H01L23/482 ,  H01L23/31

Abstract: Disclosed are embodiments of a transistor, which incorporates an airgap for low base-emitter capacitance (Cbe). Each embodiment of the transistor has a monocrystalline base and, within the monocrystalline base, an intrinsic base region and an extrinsic base region positioned laterally adjacent to the intrinsic base region, wherein the intrinsic and extrinsic base regions have co-planar top surfaces. An essentially T-shaped emitter in cross-section has a lower emitter region on the intrinsic base region and an upper emitter region above the lower emitter region. Each embodiment of the transistor further has an airgap, which is positioned laterally adjacent to the lower emitter region so as to be between the extrinsic base region and the upper emitter region. Thus, the entire airgap is above the co-planar top surfaces of the intrinsic base region and the extrinsic base region. Also disclosed herein are methods of forming the transistor embodiments.

公开(公告)号：US09859382B2

公开(公告)日：2018-01-02

申请号：US14959825

申请日：2015-12-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L29/267 ,  H01L25/00 ,  H01L25/065 ,  H01L29/20 ,  H01L29/161 ,  H01L27/092 ,  H01L29/737

CPC classification number: H01L29/267 ,  H01L21/8258 ,  H01L23/3114 ,  H01L24/19 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/092 ,  H01L29/161 ,  H01L29/20 ,  H01L29/737 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15153 ,  H01L2224/83

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated CMOS wafers and methods of manufacture. The structure includes: a chip of a first technology type comprising a trench structure on a front side; a chip of a second technology type positioned within the trench structure and embedded therein with an interlevel dielectric material; and a common wiring layer on the front side connecting to both the chip of the first technology type and the chip of the second technology type.

公开(公告)号：US09825157B1

公开(公告)日：2017-11-21

申请号：US15196920

申请日：2016-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata A. Camillo-Castillo ,  Anthony K. Stamper

IPC: H01L29/73 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/737 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7378 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor with a stress component and methods of manufacture. The heterojunction bipolar transistor includes a collector region, an emitter region and a base region. Stress material is formed within a trench of a substrate and surrounding at least the collector region and the base region.

公开(公告)号：US20170162656A1

公开(公告)日：2017-06-08

申请号：US14959825

申请日：2015-12-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L29/267 ,  H01L25/00 ,  H01L29/737 ,  H01L29/161 ,  H01L27/092 ,  H01L25/065 ,  H01L29/20

CPC classification number: H01L29/267 ,  H01L21/8258 ,  H01L23/3114 ,  H01L24/19 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/092 ,  H01L29/161 ,  H01L29/20 ,  H01L29/737 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15153 ,  H01L2224/83

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated CMOS wafers and methods of manufacture. The structure includes: a chip of a first technology type comprising a trench structure on a front side; a chip of a second technology type positioned within the trench structure and embedded therein with an interlevel dielectric material; and a common wiring layer on the front side connecting to both the chip of the first technology type and the chip of the second technology type.