公开(公告)号：US20170256462A1

公开(公告)日：2017-09-07

申请号：US15373852

申请日：2016-12-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Murat Kerem AKARVARDAR ,  Andreas KNORR

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/3083 ,  H01L21/3105 ,  H01L21/32105 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/7842 ,  H01L29/7849

Abstract: A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the fin direction and the resulting device are provided. Embodiments include forming a SiGe SRB on a substrate; forming a Si layer over the SRB; forming an NFET channel and a SiGe PFET channel in the Si layer; forming cuts through the NFET and PFET channels, respectively, and the SRB down to the substrate, the cuts formed on opposite ends of the substrate and perpendicular to the NFET and PFET channels; forming fins in the SRB and the NFET and PFET channels, the fins formed perpendicular to the cuts; forming a cut between the NFET and PFET channels, the cut formed parallel to the fins; filling the cut with oxide; and recessing the oxide down to the SRB.

公开(公告)号：US20170092764A1

公开(公告)日：2017-03-30

申请号：US14867193

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Andre LABONTE ,  Andreas KNORR

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7845 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A three-dimensional transistor includes a semiconductor substrate, a fin coupled to the substrate, the fin including an active region across a top portion thereof, the active region including a source, a drain and a channel region therebetween. The transistor further includes a gate situated above the channel region, and a gate contact situated in the active region, no portion thereof being electrically coupled to the source or drain. The transistor is achieved by removing a portion of the source/drain contact situated beneath the gate contact during fabrication.

公开(公告)号：US20160190262A1

公开(公告)日：2016-06-30

申请号：US14676608

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Andreas KNORR

IPC: H01L29/417 ,  H01L29/66 ,  H01L27/088 ,  H01L21/28 ,  H01L21/768 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate and surrounded at a lower portion thereof by a layer of isolation material, gate structure(s) and confined epitaxial material above active regions of the raised structures, the confined epitaxial material having recessed portion(s) therein. Dummy gate structures surrounding a portion of each of the raised structures are initially used, and the confined epitaxial material is created before replacing the dummy gate structures with final gate structures. The structure further includes silicide on upper surfaces of a top portion of the confined epitaxial material, and contacts above the silicide, the contacts including separate contacts electrically coupled to only one area of confined epitaxial material and common contact(s) electrically coupling two adjacent areas of the confined epitaxial material.

Abstract translation: 非平面半导体结构包括半导体衬底，耦合到衬底的多个凸起的半导体结构，并且在其下部被隔离材料层，栅极结构和凸起结构的有源区上方的限定外延材料包围， 该限制外延材料在其中具有凹入部分。 最初使用围绕每个凸起结构的一部分的虚拟门结构，并且在用最终栅极结构替换伪栅极结构之前产生约束的外延材料。 该结构还包括在限制的外延材料的顶部的上表面上的硅化物和硅化物上方的触点，触点包括电耦合到仅限于一部分的限制性外延材料的单独触点和电耦合两个相邻区域 的限制外延材料。

公开(公告)号：US20160163645A1

公开(公告)日：2016-06-09

申请号：US14563284

申请日：2014-12-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. KAMINENI ,  Ruilong XIE

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/7684 ,  H01L21/76844 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a lined bottom contact filled with conductive material. The structure further includes a layer of dielectric material surrounding sides of the lined bottom contact, a top contact on the bottom contact, the top contact having a partial liner only along sides thereof with an absence of the liner at a bottom thereof and being filled with the conductive material, and a layer of the dielectric material surrounding sides of the partially lined top contact. Fabrication of the bottom-liner free top contact includes providing a starting structure, the structure including a lined bottom contact filled with conductive material, being surrounded by a layer of dielectric material and having a planarized top surface. The method further includes creating a top layer of dielectric material above the planarized top surface, creating a layer of liner material above the top dielectric layer, creating a top contact opening to the bottom contact, lining the top contact opening with a liner material, removing the liner at a bottom of the top contact opening, exposing the bottom contact, while preserving a portion of the liner on the top dielectric layer sufficient to allow adhesion of a subsequent conductive material, and filling the contact opening with the conductive material.

Abstract translation: 半导体结构包括填充有导电材料的内衬底部接触。 所述结构还包括围绕所述衬里底部触点的侧面的介电材料层，所述底部触点上的顶部触点，所述顶部触点仅沿着其侧面具有部分衬垫，并且在其底部处不存在所述衬垫并且被填充 导电材料以及围绕部分衬里的顶部接触的侧面的电介质材料层。 底部衬垫自由顶部接触的制造包括提供起始结构，该结构包括填充有导电材料的内衬底部接触，被一层介电材料包围并具有平坦化的顶部表面。 该方法还包括在平坦化的顶部表面上方形成电介质材料的顶层，在顶部电介质层之上产生衬里材料层，形成到底部接触件的顶部接触开口，用衬里材料衬套顶部接触开口，去除 在顶部接触开口的底部处的衬垫暴露底部接触，同时保留顶部电介质层上的衬垫的一部分足以允许粘附随后的导电材料，并用导电材料填充接触开口。

公开(公告)号：US20160141489A1

公开(公告)日：2016-05-19

申请号：US14841997

申请日：2015-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan ZHANG ,  Ruilong XIE ,  Xiuyu CAI ,  Seowoo NAM ,  Hyun-Jin CHO

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L21/02 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.

Abstract translation: 提供了不使用光刻掩模形成自对准MTJ的方法和所得到的器件。 实施例包括在金属层上形成第一电极，金属层凹入低k电介质层中; 在第一电极上形成MTJ层; 在MTJ层上形成第二电极; 将所述第二电极，所述MTJ层和所述第一电极的部分去除到所述低k电介质层; 在所述第二电极和所述低k电介质层上形成氮化硅基层; 并将氮化硅基层平坦化到第二电极。