公开(公告)号：US06537891B1

公开(公告)日：2003-03-25

申请号：US09650081

申请日：2000-08-29

申请人： Charles H. Dennison ,  John K. Zahurak

发明人： Charles H. Dennison ,  John K. Zahurak

IPC分类号： H01L2176

CPC分类号： H01L27/10894 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/84 ,  H01L27/10811 ,  H01L27/10873 ,  H01L27/1203

摘要： This invention relates to the field of semiconductor integrated circuits and, particularly to stand-alone and embedded memory chips fabricated on Silicon-on-Insulator (SOI) substrates and devices. Partially depleted (PD) and fully depleted (FD) devices are utilized on the same chip. The invention is a process flow utilizing fully depleted SOI devices in one area of the chip and partially depleted SOI devices in selected other areas of the chip. The choice of fully depleted or partially depleted is solely determined by the circuit application in that specific area of the chip. The invention is able to be utilized in accordance with DRAM processing, and especially embedded DRAMs with their large proportion of associated logic circuitry.

摘要翻译： 本发明涉及半导体集成电路领域，特别涉及制造在绝缘体上硅（SOI）衬底和器件上的独立和嵌入式存储器芯片。 部分耗尽（PD）和完全耗尽（FD）器件在同一芯片上被利用。 本发明是在芯片的一个区域中利用完全耗尽的SOI器件和在芯片的选定其他区域中部分耗尽的SOI器件的工艺流程。 完全耗尽或部分耗尽的选择仅由芯片的该特定区域中的电路应用决定。 本发明能够根据DRAM处理，特别是具有大比例的相关逻辑电路的嵌入式DRAM。

公开(公告)号：US06383887B1

公开(公告)日：2002-05-07

申请号：US09724752

申请日：2000-11-28

申请人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

发明人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

IPC分类号： H01L2120

CPC分类号： H01L27/10888 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L29/94 ,  Y10S438/964

摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively lo forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.

摘要翻译： 本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。 本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）基本上选择性地从暴露的未掺杂硅而不是暴露的掺杂硅形成凹凸多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。 本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的坚固的多晶硅和掺杂的非坚固的多晶硅。

公开(公告)号：US06372601B1

公开(公告)日：2002-04-16

申请号：US09146838

申请日：1998-09-03

申请人： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

发明人： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

IPC分类号： H01L21762

CPC分类号： H01L21/76232 ,  H01L21/0332 ,  H01L21/76235

摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

公开(公告)号：US06261899B1

公开(公告)日：2001-07-17

申请号：US09087114

申请日：1998-05-29

申请人： Richard H. Lane ,  John K. Zahurak

发明人： Richard H. Lane ,  John K. Zahurak

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/1052 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

摘要： In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate. The upper insulating layer is etched relative to the interposed conductive layer to form a capacitor container first portion. Subsequently, the interposed conductive layer is etched to form a capacitor container second portion.

公开(公告)号：US06180485B2

公开(公告)日：2001-01-30

申请号：US09323596

申请日：1999-06-01

申请人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

发明人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

IPC分类号： H01L2120

CPC分类号： H01L27/10888 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L29/94 ,  Y10S438/964

摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.

摘要翻译： 本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。 本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）从暴露的未掺杂的硅而不是暴露的掺杂的硅基本上选择性地形成坚固的多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。 本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的坚固的多晶硅和掺杂的非坚固的多晶硅。

公开(公告)号：US06175146B1

公开(公告)日：2001-01-16

申请号：US08970345

申请日：1997-11-14

申请人： Richard H. Lane ,  John K. Zahurak

发明人： Richard H. Lane ,  John K. Zahurak

IPC分类号： H01L2358

CPC分类号： H01L27/10852 ,  H01L27/1052 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

摘要： In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate. The upper insulating layer is etched relative to the interposed conductive layer to form a capacitor container first portion. Subsequently, the interposed conductive layer is etched to form a capacitor container second portion.

摘要翻译： 一方面，本发明提供一种形成集成电路存储器件的方法。 在一个优选实施例中，在两个存储器阵列区域和外围电路区域上形成导电层。 在导电层上形成难熔金属层，以在两个区域提供导电结构。 根据该实施方式的优选方案，形成在存储器阵列上方的导电层为要形成的电容器容器提供电接触。 根据该实施方案的另一个优选方面，形成在外围电路区域上的导电层构成包括至少一些硅化物的导电线。 在另一个优选实施方式中，本发明提供了一种在衬底上形成电容器容器的方法。 根据该实施方式的优选方案，在衬底上方的上绝缘层和下导电层之间，导电层被竖立地插入。 相对于插入的导电层蚀刻上绝缘层以形成电容器容器第一部分。 随后，蚀刻插入的导电层以形成电容器容器第二部分。

公开(公告)号：US6090655A

公开(公告)日：2000-07-18

申请号：US26355

申请日：1998-02-19

申请人： John K. Zahurak ,  Richard H. Lane

发明人： John K. Zahurak ,  Richard H. Lane

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/82 ,  H01L28/84

摘要： Disclosed is a three-dimensional integrated memory cell having a high interior volume and a method for constructing the same. The cell makes use of a highly conductive substrate material for the bottom electrode, allowing construction of a thin substrate without intolerable resistance. The substrate of the preferred embodiment, for example, comprises titanium silicide. The preferred method comprises conformal deposition of a thin polysilicon layer within a high aspect ratio container, followed by deposition of a suitable metal for silicidation with the polysilicon layer. The metal need not be conformal for this preferred method and may be deposited by sputter deposition. After silicidation, excess metal is selectively etched away to leave a conformal, thin yet highly conductive substrate material. The greater volume available due to this thinner substrate permits either scaling down of the cell dimension for more dense arrays with maintained capacitance per memory cell, or use of larger microstructures over the bottom electrode substrate, such as hemispherical grained silicon layers, for increased electrode surface area and greater capacitance.

摘要翻译： 公开了具有高内部容积的三维集成存储单元及其构造方法。 该电池利用用于底部电极的高导电性基板材料，可以构造薄的基板，而不会产生不可耐受的电阻。 例如，优选实施例的衬底包括硅化钛。 优选的方法包括在高纵横比容器内共形沉积薄多晶硅层，随后沉积合适的金属以与多晶硅层进行硅化。 对于该优选方法，金属不需要保形，并且可以通过溅射沉积来沉积。 在硅化后，选择性地蚀刻掉多余的金属以留下保形，薄而高度导电的基底材料。 由于这种较薄的衬底，可用的较大的体积允许针对更密集的阵列缩小电池尺寸以保持每个存储器单元的电容，或者在底部电极衬底（例如半球形晶粒硅层）上使用较大的微结构用于增加电极表面 面积和更大的电容。

公开(公告)号：US5998257A

公开(公告)日：1999-12-07

申请号：US816621

申请日：1997-03-13

申请人： Richard H. Lane ,  John K. Zahurak

发明人： Richard H. Lane ,  John K. Zahurak

IPC分类号： H01L21/8239 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L27/1052 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

摘要： In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate. The upper insulating layer is etched relative to the interposed conductive layer to form a capacitor container first portion. Subsequently, the interposed conductive layer is etched to form a capacitor container second portion.

公开(公告)号：US08665630B2

公开(公告)日：2014-03-04

申请号：US13117889

申请日：2011-05-27

申请人： Roy E. Meade ,  John K. Zahurak

发明人： Roy E. Meade ,  John K. Zahurak

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0069

摘要： Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge of the capacitor through a resistive switching element of the memory cell.

摘要翻译： 描述与存储器单元操作相关联的方法，设备和系统。 操作存储器单元的一种或多种方法包括将耦合到存储器单元的电容器充电到特定的电压电平，并通过控制存储器的电阻式开关元件的电容放电来将存储器单元从第一状态编程到第二状态 细胞。

公开(公告)号：US08535992B2

公开(公告)日：2013-09-17

申请号：US12826323

申请日：2010-06-29

申请人： Sanh D. Tang ,  John K. Zahurak ,  Michael P. Violette

发明人： Sanh D. Tang ,  John K. Zahurak ,  Michael P. Violette

IPC分类号： H01L21/322

CPC分类号： H01L29/66363 ,  H01L27/1027 ,  H01L29/42308 ,  H01L29/74 ,  H01L2924/1301

摘要： Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

摘要翻译： 显示存储器件和制造存储器件的方法。 所示的方法和配置提供用于增加存储器密度的折叠和垂直存储器件。 提供的方法减少了对诸如深掺杂剂植入物的制造方法的需要。