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143 条记录 (耗时 0.025 秒)

    MEMORY CELL OPERATION
    1.
    发明申请
    MEMORY CELL OPERATION 有权
    记忆体操作

    公开(公告)号：US20120300530A1

    公开(公告)日：2012-11-29

    申请号：US13117889

    申请日：2011-05-27

    申请人： Roy E. Meade ,  John K. Zahurak

    发明人： Roy E. Meade ,  John K. Zahurak

    IPC分类号： G11C11/21

    CPC分类号： G11C7/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0069

    摘要： Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge of the capacitor through a resistive switching element of the memory cell.

    摘要翻译： 描述与存储器单元操作相关联的方法，设备和系统。 操作存储器单元的一种或多种方法包括将耦合到存储器单元的电容器充电到特定的电压电平，并通过控制存储器的电阻式开关元件的电容放电来将存储器单元从第一状态编程到第二状态 细胞。

    Memory cell operation including capacitance
    2.
    发明授权
    Memory cell operation including capacitance 有权
    存储单元操作，包括电容

    公开(公告)号：US08665630B2

    公开(公告)日：2014-03-04

    申请号：US13117889

    申请日：2011-05-27

    申请人： Roy E. Meade ,  John K. Zahurak

    发明人： Roy E. Meade ,  John K. Zahurak

    IPC分类号： G11C11/00

    CPC分类号： G11C7/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0069

    摘要： Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge of the capacitor through a resistive switching element of the memory cell.

    摘要翻译： 描述与存储器单元操作相关联的方法，设备和系统。 操作存储器单元的一种或多种方法包括将耦合到存储器单元的电容器充电到特定的电压电平，并通过控制存储器的电阻式开关元件的电容放电来将存储器单元从第一状态编程到第二状态 细胞。

    Methods of forming recessed access devices associated with semiconductor constructions
    7.
    发明授权
    Methods of forming recessed access devices associated with semiconductor constructions 有权
    形成与半导体结构相关联的凹陷接入设备的方法

    公开(公告)号：US08067286B2

    公开(公告)日：2011-11-29

    申请号：US13012675

    申请日：2011-01-24

    申请人： Kunal R. Parekh ,  Suraj J. Mathew ,  Jigish D. Trivedi ,  John K. Zahurak ,  Sanh D. Tang

    发明人： Kunal R. Parekh ,  Suraj J. Mathew ,  Jigish D. Trivedi ,  John K. Zahurak ,  Sanh D. Tang

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10876 ,  H01L27/10823

    摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.

    摘要翻译： 本发明包括形成凹入进入装置的方法。 提供基板以在其中具有凹入的接入装置沟槽。 一对凹进的接入设备沟槽彼此相邻。 导电材料形成在凹进的存取装置沟槽内，源极/漏极区域靠近导电材料形成。 导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。 在凹陷的访问设备沟槽形成在衬底内之后，在相邻的凹进的访问设备之间形成隔离区沟槽，并且填充有电绝缘材料以形成沟槽隔离区域。

    Localized biasing for silicon on insulator structures
    8.
    发明授权
    Localized biasing for silicon on insulator structures 有权
    硅绝缘体结构的局部偏置

    公开(公告)号：US07659152B2

    公开(公告)日：2010-02-09

    申请号：US10930001

    申请日：2004-08-30

    申请人： Fernando Gonzalez ,  John K. Zahurak

    发明人： Fernando Gonzalez ,  John K. Zahurak

    IPC分类号： H01L21/84

    CPC分类号： H01L21/84 ,  H01L27/0214 ,  H01L27/10858 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.

    摘要翻译： 绝缘体上硅器件具有形成在SOI的绝缘体层中的局部偏置结构。 局部偏置结构包括图案化导体，其向SOI的硅层的不同区域提供偏置信号。 导体凹陷到绝缘体层中以提供与硅层基本平坦的界面。 导体连接到偏置电压源。 在一个实施例中，提供分别连接到多个电压源的多个导体。 因此，硅层的不同区域被不同的偏置信号偏置。

    LOCALIZED BIASING FOR SILICON ON INSULATOR STRUCTURES
    9.
    发明申请
    LOCALIZED BIASING FOR SILICON ON INSULATOR STRUCTURES 有权
    绝缘子结构中硅的局部偏置

    公开(公告)号：US20100012995A1

    公开(公告)日：2010-01-21

    申请号：US12565294

    申请日：2009-09-23

    申请人： Fernando Gonzalez ,  John K. Zahurak

    发明人： Fernando Gonzalez ,  John K. Zahurak

    IPC分类号： H01L27/108 ,  H01L29/06

    CPC分类号： H01L21/84 ,  H01L27/0214 ,  H01L27/10858 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.

    摘要翻译： 绝缘体上硅器件具有形成在SOI的绝缘体层中的局部偏置结构。 局部偏置结构包括图案化导体，其向SOI的硅层的不同区域提供偏置信号。 导体凹陷到绝缘体层中以提供与硅层基本平坦的界面。 导体连接到偏置电压源。 在一个实施例中，提供分别连接到多个电压源的多个导体。 因此，硅层的不同区域被不同的偏置信号偏置。