公开(公告)号：US20060118859A1

公开(公告)日：2006-06-08

申请号：US11330660

申请日：2006-01-12

申请人： Jae-Hwang Kim ,  Hee-Seog Jeon

发明人： Jae-Hwang Kim ,  Hee-Seog Jeon

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

摘要： A memory cell and a method for fabricating same. The memory cell comprises a source region and a drain region formed in a semiconductor substrate and a channel region defined between the source and drain regions. Charge storage layers are formed the channel region. A gate insulating layer is formed on the channel region between the charge storage layers, and a gate electrode is formed on the gate insulating layer and the charge trapping storage layers.

摘要翻译： 一种存储单元及其制造方法。 存储单元包括形成在半导体衬底中的源极区域和漏极区域以及限定在源极和漏极区域之间的沟道区域。 电荷存储层形成沟道区。 在电荷存储层之间的沟道区域上形成栅极绝缘层，并且在栅极绝缘层和电荷俘获存储层上形成栅电极。

公开(公告)号：US09330745B2

公开(公告)日：2016-05-03

申请号：US14509756

申请日：2014-10-08

申请人： Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Hee-Seog Jeon

发明人： Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Hee-Seog Jeon

IPC分类号： G11C11/16

CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.

摘要翻译： 磁存储器件包括分别耦合到第一和第二位线的第一和第二磁存储器单元。 第一和第二磁存储单元分别包括钉扎磁性层，自由磁性层和隧道绝缘层。 固定磁性层，隧道绝缘层和自由磁性层的各个堆叠顺序在第一和第二磁性存储单元中是不同的。 磁存储器件还包括至少一个晶体管，其被配置为将第一和第二磁存储器单元耦合到公共源极线。 还讨论了相关的操作方法。

公开(公告)号：US08432742B2

公开(公告)日：2013-04-30

申请号：US13114120

申请日：2011-05-24

申请人： Chang-Min Jeong ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Ji-Do Ryu

发明人： Chang-Min Jeong ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Ji-Do Ryu

IPC分类号： G11C11/34

CPC分类号： G11C16/06 ,  G11C16/0483

摘要： A non-volatile memory cell array, comprising sector selection transistors controlled by a voltage applied to sector selection lines, first through fourth memory cells connected in series to the sector selection transistors, a first common source line connected between the first memory cell and the second memory cell, and a second common source line connected between the third memory cell and the fourth memory cell and separated from the first common source line. A first voltage is applied to the first common source line, and a second voltage different from the first voltage is applied to the second common source line.

摘要翻译： 一种非易失性存储单元阵列，包括由施加到扇区选择线的电压控制的扇区选择晶体管，与扇区选择晶体管串联连接的第一至第四存储器单元，连接在第一存储单元与第二存储单元之间的第一公共源极线 以及连接在第三存储单元和第四存储单元之间并与第一公共源极线分离的第二公共源极线。 向第一公共源极线施加第一电压，并且将不同于第一电压的第二电压施加到第二公共源极线。

公开(公告)号：US20120181607A1

公开(公告)日：2012-07-19

申请号：US13352194

申请日：2012-01-17

申请人： Ji-Do Ryu ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Yong-Suk Choi

发明人： Ji-Do Ryu ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Yong-Suk Choi

IPC分类号： H01L27/088

CPC分类号： H01L29/42328 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/11504 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L29/7883

摘要： A semiconductor device includes an active region in a substrate, first to third gate structures crossing the active region and sequentially arranged parallel to each other, a first doped region in the active region between the first and second gate structures and having a first horizontal width and a first depth, and a second doped region in the active region between the second and third gate structures and having a second horizontal width and a second depth. The second horizontal width is larger than the first horizontal width and the second depth is shallower than the first depth. A distance between the first and second gate structures adjacent to each other is smaller than that between the second and third gate structures adjacent to each other. Related fabrication methods are also described.

摘要翻译： 半导体器件包括在衬底中的有源区域，与有源区域交叉并顺序地彼此平行布置的第一至第三栅极结构，位于第一和第二栅极结构之间的有源区域中的第一掺杂区域，并且具有第一水平宽度和 第一深度和在第二和第三栅极结构之间的有源区域中的第二掺杂区域，并且具有第二水平宽度和第二深度。 第二水平宽度大于第一水平宽度，第二深度比第一深度浅。 彼此相邻的第一和第二栅极结构之间的距离小于彼此相邻的第二和第三栅极结构之间的距离。 还描述了相关的制造方法。

公开(公告)号：US08111553B2

公开(公告)日：2012-02-07

申请号：US12662431

申请日：2010-04-16

申请人： Bo-Young Seo ,  Hee-Seog Jeon ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Myung-Jo Chun

发明人： Bo-Young Seo ,  Hee-Seog Jeon ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Myung-Jo Chun

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C16/0433 ,  G11C16/24

摘要： A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited.

摘要翻译： 提供了能够减少编程干扰的非易失性半导体存储器件及其编程方法。 连接到与选择的存储单元相同的块中的未选择的存储单元的位线通过使位线选择开关失活而进入浮置状态，使得形成在第一导电类型沟道和源极/漏极端子中的电压电平 在存储晶体管之下的凹穴第二导电类型具有选择线的电压电平的中间电平和口袋P型。 因此，可以抑制由FN隧穿和结热电子引起的程序干扰。

公开(公告)号：US20090239349A1

公开(公告)日：2009-09-24

申请号：US12476698

申请日：2009-06-02

申请人： Kwang-Wook Koh ,  Hee-Seog Jeon

发明人： Kwang-Wook Koh ,  Hee-Seog Jeon

IPC分类号： H01L21/76

CPC分类号： H01L27/11524 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521

摘要： In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

摘要翻译： 在非易失性存储器件及其制造方法中，形成在半导体衬底中限定有源区的器件隔离层。 在半导体衬底上形成栅绝缘层和第一导电层。 形成一对堆叠图案，每一个在第一导电层上具有隔间电介质层图案和第二导电层图案。 在堆叠图案之间的第一导电层图案上形成掩模图案，掩模图案与每个堆叠图案间隔开。 使用堆叠图案和掩模图案作为蚀刻掩模来图案化第一导电层。 将杂质离子注入到有源区中以形成一对非易失性存储晶体管和选择晶体管。 所得到的非易失性存储器件包括包括一对非易失性存储晶体管和选择晶体管的存储单元单元。

公开(公告)号：US20090194815A1

公开(公告)日：2009-08-06

申请号：US12339448

申请日：2008-12-19

申请人： Sung-Gon CHOI ,  Hee-Seog Jeon

发明人： Sung-Gon CHOI ,  Hee-Seog Jeon

IPC分类号： H01L29/78 ,  H01L27/092

CPC分类号： H01L29/0847 ,  H01L21/76895 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/7835

摘要： A high voltage transistor that includes a substrate where an active region is defined, a first impurity region and a second impurity region in the active region and a third impurity region between the first and second impurity regions, and a first gate electrode on the active region between the first impurity region and the third impurity region and a second gate electrode on the active region between the second impurity region and the third impurity region.

摘要翻译： 一种高电压晶体管，包括限定有源区的衬底，所述有源区中的第一杂质区和第二杂质区以及所述第一和第二杂质区之间的第三杂质区，以及所述有源区上的第一栅电极 在第一杂质区域和第三杂质区域之间的有源区域上的第二栅电极和第二杂质区域之间的有源区域上的第二栅电极。

公开(公告)号：US07557404B2

公开(公告)日：2009-07-07

申请号：US11704003

申请日：2007-02-08

申请人： Kwang-Wook Koh ,  Hee-Seog Jeon

发明人： Kwang-Wook Koh ,  Hee-Seog Jeon

IPC分类号： H01L29/788

CPC分类号： H01L27/11524 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521

摘要： In a nonvolatile memory device and a method of fabricating the same, the nonvolatile memory device may include a semiconductor substrate having a device isolation layer defining an active region, a pair of nonvolatile memory transistors on the active region, a select transistor disposed between the pair of nonvolatile memory transistors, and floating diffusion regions on the active region between each of the nonvolatile memory transistors and the select transistor. The select transistor may include a gate insulation layer having a thickness and a material that are the same as those of gate insulation layers of the nonvolatile memory transistors. The resulting nonvolatile memory device may include a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

摘要翻译： 在非易失性存储器件及其制造方法中，非易失性存储器件可包括具有限定有源区的器件隔离层的半导体衬底，有源区上的一对非易失性存储晶体管，位于该对之间的选择晶体管 的非易失性存储晶体管，以及在每个非易失性存储晶体管和选择晶体管之间的有源区上的浮动扩散区。 选择晶体管可以包括具有与非易失性存储晶体管的栅极绝缘层相同的厚度和材料的栅极绝缘层。 所得到的非易失性存储器件可以包括包括一对非易失性存储晶体管和选择晶体管的存储单元单元。

公开(公告)号：US20090065845A1

公开(公告)日：2009-03-12

申请号：US12230938

申请日：2008-09-08

申请人： Young-Ho Kim ,  Hee-Seog Jeon ,  Yong-Kyu Lee

发明人： Young-Ho Kim ,  Hee-Seog Jeon ,  Yong-Kyu Lee

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529 ,  H01L29/665 ,  H01L29/7833

摘要： Provided are an embedded semiconductor device and a method of manufacturing an embedded semiconductor device. In a method of manufacturing the embedded semiconductor device, layers of at least one cell gate stack may be formed in a cell area of a substrate. A logic gate structure may be formed in a logic area of the substrate. First source/drain regions may be formed adjacent to the logic gate structure, and metal silicide patterns may be formed on the logic gate structure and the first source/drain regions. At least one hard mask may be formed on the layers of the at least one cell gate stack, and a blocking pattern may be formed to cover the logic gate structure and the first source/drain regions. The at least one cell gate stack may be formed in the cell area by etching the layers of the at least one cell gate stack using the at least one hard mask as an etching mask. A memory transistor in the cell area may have an increased integration degree and a logic transistor in the logic area may have an increased response speed and a decreased resistance.

摘要翻译： 提供了嵌入式半导体器件和制造嵌入式半导体器件的方法。 在制造嵌入式半导体器件的方法中，可以在衬底的单元区域中形成至少一个单元栅极堆叠的层。 逻辑门结构可以形成在衬底的逻辑区域中。 可以在逻辑门结构附近形成第一源极/漏极区，并且可以在逻辑门结构和第一源极/漏极区上形成金属硅化物图案。 可以在至少一个单元栅极堆叠的层上形成至少一个硬掩模，并且可以形成阻挡图案以覆盖逻辑门结构和第一源极/漏极区域。 可以通过使用至少一个硬掩模作为蚀刻掩模来蚀刻至少一个单元栅极堆叠的层而在单元区域中形成至少一个单元栅极堆叠。 单元区域中的存储晶体管可以具有增加的积分度，并且逻辑区域中的逻辑晶体管可以具有增加的响应速度和降低的电阻。

公开(公告)号：US20080179692A1

公开(公告)日：2008-07-31

申请号：US12013618

申请日：2008-01-14

申请人： Myung-Jo Chun ,  Hee-Seog Jeon ,  Yong-Kyu Lee ,  Young-Ho Kim

发明人： Myung-Jo Chun ,  Hee-Seog Jeon ,  Yong-Kyu Lee ,  Young-Ho Kim

IPC分类号： H01L27/112 ,  H01L21/8234

CPC分类号： H01L27/11293 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11266 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665

摘要： A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including the same conductivity type as that of the first impurity region is formed at the off-cell region of the substrate so as to be spaced apart from a sidewall of the second gate electrode. A fourth impurity region is formed at the off-cell region to extend from the second impurity region and to overlap with the sidewall of the second gate electrode. The fourth impurity region has a conductivity type opposite to that of the second impurity region and a depth greater than that of the second impurity region.

摘要翻译： 掩模只读存储器（MROM）器件分别包括形成在衬底的单元和离子区域的第一和第二栅电极。 第一杂质区形成在基板的单电池区域上，以便与第一栅电极相邻。 形成与第一杂质区相同导电类型的第二杂质区，以与第二栅电极的侧壁间隔开。 第四杂质区形成在离电池区域，从第二杂质区延伸并与第二栅电极的侧壁重叠。 第四杂质区域具有与第二杂质区域相反的导电类型，并且深度大于第二杂质区域的深度。