公开(公告)号：US08014224B2

公开(公告)日：2011-09-06

申请号：US12201024

申请日：2008-08-29

申请人： Kenji Yoshinaga ,  Fukashi Morishita

发明人： Kenji Yoshinaga ,  Fukashi Morishita

IPC分类号： G11C5/14

CPC分类号： G11C5/147

摘要： There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.

摘要翻译： 提供了由内部发电电路产生的内部电力提供的半导体器件，以执行稳定的操作，并且还抑制功耗。 控制电路，行/列解码器和读出放大器由内部降压电压驱动。 另一方面，具有高功耗的数据路径由外部电源电压驱动。 电平转换电路接收具有外部电源电压的电压电平的地址信号或指令信号，将电压电平转换为内部降压电压，并将结果信号输出到控制电路。 电平转换电路从控制电路接收具有内部降压电压的电压电平的控制信号，将电压电平转换为外部电源电压，并将结果信号输出到数据路径。

公开(公告)号：US20110182131A1

公开(公告)日：2011-07-28

申请号：US13080114

申请日：2011-04-05

申请人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

发明人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

IPC分类号： G11C5/14

CPC分类号： G05F1/468 ,  G11C5/025 ,  G11C5/147

摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。

公开(公告)号：US20100231768A1

公开(公告)日：2010-09-16

申请号：US12722121

申请日：2010-03-11

申请人： Hiroto Utsunomiya ,  Katsumi Dosaka ,  Hiroshi Kato ,  Fukashi Morishita ,  Fumiyasu Sasaki

发明人： Hiroto Utsunomiya ,  Katsumi Dosaka ,  Hiroshi Kato ,  Fukashi Morishita ,  Fumiyasu Sasaki

IPC分类号： H04N5/335

CPC分类号： H04N5/37455 ,  H03M1/1205 ,  H03M1/144 ,  H03M1/403 ,  H03M1/66 ,  H03M2201/16 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3765 ,  H04N5/378

摘要： There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

摘要翻译： 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。

公开(公告)号：US20100188120A1

公开(公告)日：2010-07-29

申请号：US12677745

申请日：2008-09-19

申请人： Fukashi Morishita

发明人： Fukashi Morishita

IPC分类号： H03K19/0944

CPC分类号： H01L27/1203 ,  H01L27/088 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L29/7841 ,  H01L29/78615

摘要： The present invention provides a semiconductor integrated circuit device in which characteristics of an SOI transistor are effectively used to achieve higher speed, higher degree of integration, and also reduction in voltage and power consumption. The semiconductor integrated circuit device according to the present invention has a configuration in which a plurality of external power supply lines and body voltage control lines are alternately arranged in one direction so as to extend over the entire chip, which supply power and a body voltage to logic circuits, an analog circuit and memory circuits. A body voltage control type logic gate is fully applied in the logic circuit, whereas the body voltage control type logic gate is partially applied in the memory circuit.

摘要翻译： 本发明提供一种半导体集成电路器件，其中SOI晶体管的特性被有效地用于实现更高的速度，更高的集成度，并且还降低了电压和功耗。 根据本发明的半导体集成电路器件具有这样的结构，其中多个外部电源线和体电压控制线在一个方向上交替布置，以便在整个芯片上延伸，从而将电源和体电压提供给 逻辑电路，模拟电路和存储器电路。 体电压控制型逻辑门完全应用在逻辑电路中，而体电压控制型逻辑门部分地应用于存储器电路中。

公开(公告)号：US07498207B2

公开(公告)日：2009-03-03

申请号：US11902996

申请日：2007-09-27

申请人： Masakazu Hirose ,  Fukashi Morishita

发明人： Masakazu Hirose ,  Fukashi Morishita

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/10873 ,  G11C11/404 ,  G11C11/4085 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/0218 ,  H01L27/10808 ,  H01L27/10817 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/78612

摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

摘要翻译： 在该半导体存储器件中，在绝缘层中设置不形成有绝缘层的电位钳位区域。 更具体地，电位钳位区域形成在靠近第一杂质区域的位置的主体部分下方，并延伸到第一半导体层。 主体固定部分形成在主体部分和电位夹紧区域之间的边界区域中。 在SOI（绝缘体上硅）结构中形成DRAM单元的情况下，这种结构能够提高操作性能而不增加布局面积。

公开(公告)号：US07408818B2

公开(公告)日：2008-08-05

申请号：US11703672

申请日：2007-02-08

申请人： Kenji Yoshinaga ,  Masashi Matsumura ,  Futoshi Igaue ,  Mihoko Akiyama ,  Fukashi Morishita

发明人： Kenji Yoshinaga ,  Masashi Matsumura ,  Futoshi Igaue ,  Mihoko Akiyama ,  Fukashi Morishita

IPC分类号： G11C11/34

CPC分类号： G11C29/48 ,  G11C29/12 ,  G11C29/12005

摘要： A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.

摘要翻译： 半导体器件具有第一操作模式和第二操作模式，其中提供具有比第一操作模式中更高的电压值的电源。 半导体器件包括具有用于存储数据的存储单元的存储器部分和向存储器部分提供第一电压和第二电压的电源电路部分。 存储器部分基于第一电压和第二电压将数据写入或从存储器单元读取数据，并且电源电路部分在第二操作模式中在第一电压和第二电压之间提供较小的电压差，与第 在第一操作模式下的电压差。

公开(公告)号：US20080023743A1

公开(公告)日：2008-01-31

申请号：US11905002

申请日：2007-09-27

申请人： Masakazu Hirose ,  Fukashi Morishita

发明人： Masakazu Hirose ,  Fukashi Morishita

IPC分类号： H01L27/108

CPC分类号： H01L27/10873 ,  G11C11/404 ,  G11C11/4085 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/0218 ,  H01L27/10808 ,  H01L27/10817 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/78612

摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

摘要翻译： 在该半导体存储器件中，在绝缘层中设置不形成有绝缘层的电位钳位区域。 更具体地，电位钳位区域形成在靠近第一杂质区域的位置的主体部分下方，并延伸到第一半导体层。 主体固定部分形成在主体部分和电位夹紧区域之间的边界区域中。 在SOI（绝缘体上硅）结构中形成DRAM单元的情况下，这种结构能够提高操作性能而不增加布局面积。

公开(公告)号：US20060285576A1

公开(公告)日：2006-12-21

申请号：US11452317

申请日：2006-06-14

申请人： Takayuki Gyoten ,  Fukashi Morishita ,  Katsumi Dosaka

发明人： Takayuki Gyoten ,  Fukashi Morishita ,  Katsumi Dosaka

IPC分类号： G01K7/00 ,  H05B1/02

CPC分类号： G01K7/01

摘要： There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals.

摘要翻译： 提供了能够高精度地检测半导体器件的温度的技术。 检测半导体器件的温度的温度检测电路包括：第一短周期振荡器，其产生相对于频率具有正温度特性的第一时钟信号;第二短周期振荡器，产生具有负温度特性的第二时钟信号 以及温度信号生成单元，其基于第一和第二时钟信号产生根据半导体器件的温度而变化的温度信号。

公开(公告)号：US07030681B2

公开(公告)日：2006-04-18

申请号：US10118432

申请日：2002-04-09

申请人： Akira Yamazaki ,  Fukashi Morishita ,  Yasuhiko Taito ,  Nobuyuki Fujii ,  Mako Okamoto

发明人： Akira Yamazaki ,  Fukashi Morishita ,  Yasuhiko Taito ,  Nobuyuki Fujii ,  Mako Okamoto

IPC分类号： G05F1/10

CPC分类号： G11C5/146

摘要： Well bias voltages are generated in accordance with a logic power supply voltage and a memory power supply voltage. The transistor included in a control circuit in a memory core is constituted of a logic transistor manufactured through the same manufacturing steps as those for the transistors of a logic formed on the same semiconductor substrate. Well bias voltages (VBB, VPP) are applied to a back gate of this logic transistor. A memory integrated with a logic on a common semiconductor substrate is provided which allows a transistor of a control circuit therein to be manufactured through the same manufacturing process as that of the logic and allows reduction of current consumption.

公开(公告)号：US20050280465A1

公开(公告)日：2005-12-22

申请号：US11210845

申请日：2005-08-25

申请人： Fukashi Morishita

发明人： Fukashi Morishita

IPC分类号： H02J1/00 ,  G05F1/46 ,  G05F3/24 ,  G11C11/407 ,  H05B37/02

CPC分类号： G05F1/465

摘要： An internal power supply voltage generation circuit includes a main amplifier that supplies a current from an external power supply node to an internal power supply line in accordance with the difference between a reference voltage from a reference voltage generation circuit and an internal power supply voltage on the internal power supply line. The current supply amount by the main amplifier is adjusted by a level adjust circuit, according to the difference between the external power supply voltage and the reference voltage. The internal power supply voltage generation circuit can suppress reduction in the internal power supply voltage in the vicinity of the lower limit area of the differential power supply voltage.

摘要翻译： 内部电源电压产生电路包括主放大器，该主放大器根据来自基准电压产生电路的参考电压和内部电源电压之间的差，从外部电源节点向内部电源线提供电流 内部电源线。 根据外部电源电压和参考电压之间的差异，通过电平调整电路调整主放大器的电流供给量。 内部电源电压产生电路可以抑制差分电源电压的下限区域附近的内部电源电压的降低。