公开(公告)号：US4597062A

公开(公告)日：1986-06-24

申请号：US630863

申请日：1984-07-16

申请人： Masamichi Asano ,  Hiroshi Iwahashi

发明人： Masamichi Asano ,  Hiroshi Iwahashi

IPC分类号： G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/30 ,  G11C29/34 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C29/34

摘要： A non-volatile semiconductor memory system includes a memory cell array having floating gate type MOS transistors, and a boosting circuit for boosting a write voltage applied to the memory system. A distributing circuit is further contained for selectively distributing a boosted voltage from the boosting circuit to at least a part of the memory system, for example, row lines in response to a control signal.

摘要翻译： 非易失性半导体存储器系统包括具有浮置栅型MOS晶体管的存储单元阵列和用于升压施加到存储器系统的写入电压的升压电路。 还包括分配电路，用于响应于控制信号选择性地将升压电压从升压电路分配到存储器系统的至少一部分，例如行线。

公开(公告)号：US4506350A

公开(公告)日：1985-03-19

申请号：US353515

申请日：1982-03-01

申请人： Masamichi Asano ,  Hiroshi Iwahashi

发明人： Masamichi Asano ,  Hiroshi Iwahashi

IPC分类号： G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/30 ,  G11C29/34 ,  G11C11/40

CPC分类号： G11C16/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C29/34

摘要： A non-volatile semiconductor memory system includes a memory cell array having floating gate type MOS transistors, and a boosting circuit for boosting a write voltage applied to the memory system. A distributing circuit is further contained for selectively distributing a boosted voltage from the boosting circuit to at least a part of the memory system, for example, row lines in response to a control signal.

公开(公告)号：US4495693A

公开(公告)日：1985-01-29

申请号：US487765

申请日：1983-04-22

申请人： Hiroshi Iwahashi ,  Masamichi Asano ,  Kuniyoshi Yoskikawa ,  Masazi Mito

发明人： Hiroshi Iwahashi ,  Masamichi Asano ,  Kuniyoshi Yoskikawa ,  Masazi Mito

IPC分类号： H01L21/8247 ,  H01L27/088 ,  H01L27/10 ,  H01L27/105 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： H01L29/4238 ,  H01L27/088 ,  H01L27/11526 ,  H01L29/7881 ,  H01L27/105

摘要： A nonvolatile semiconductor memory device is provided having a MOS transistor and a floating gate type MOS transistor. The length of an overlap between a floating gate and a drain region of the floating gate type MOS transistor is made smaller than that of an overlap between the gate and the drain region of the MOS transistor.

摘要翻译： 提供一种具有MOS晶体管和浮动栅型MOS晶体管的非易失性半导体存储器件。 使浮置型MOS晶体管的浮置栅极和漏极区域之间的重叠的长度小于MOS晶体管的栅极和漏极区域之间的重叠的长度。

公开(公告)号：US5761119A

公开(公告)日：1998-06-02

申请号：US273922

申请日：1994-07-12

申请人： Masamichi Asano

发明人： Masamichi Asano

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/10 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

CPC分类号： H01L27/115 ,  G11C16/10 ,  G11C16/16 ,  H01L29/42328

摘要： A non-volatile semiconductor memory cell including: a plurality of blocks each having a plurality of floating gate transistors as memory cells, the floating gate transistor having a drain, a source, a floating gate, and a control gate capacitively coupled to the floating gate, and a data program of the floating gate transistor being effected by data write through injection of electrons into the floating gate and by data erase through emission of electrons from the floating gates; a circuit unit for applying an erase signal to a selected one of the blocks to emit electrons from the floating gates of a plurality of memory cells in the selected block and to erase data in all of the memory cells in the selected block at the same time; and a circuit unit for applying a write signal to the drains of the floating gate transistors within the selected block, without applying the write signal to the drains of the floating gate transistors of non-selected blocks.

摘要翻译： 一种非易失性半导体存储单元，包括：多个块，每个块具有作为存储单元的多个浮置栅极晶体管，所述浮置栅极晶体管具有漏极，源极，浮置栅极和与所述浮动栅极电容耦合的控制栅极 并且浮栅晶体管的数据程序通过通过将电子注入到浮置栅中的数据写入和通过从浮置栅极发射电子的数据擦除来实现; 电路单元，用于将擦除信号施加到所选块中的一个块，以从所选块中的多个存储单元的浮动栅极发射电子，并同时擦除所选块中的所有存储单元中的数据 ; 以及电路单元，用于将写信号施加到所选块内的浮栅晶体管的漏极，而不将写信号施加到未选块的浮栅晶体管的漏极。

公开(公告)号：US5257230A

公开(公告)日：1993-10-26

申请号：US565820

申请日：1990-08-13

申请人： Kazuhiko Nobori ,  Taira Iwase ,  Masamichi Asano ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuo Yonehara ,  Satoshi Nikawa ,  Koji Saito

发明人： Kazuhiko Nobori ,  Taira Iwase ,  Masamichi Asano ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuo Yonehara ,  Satoshi Nikawa ,  Koji Saito

IPC分类号： H01L21/82 ,  G11C29/00 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/10 ,  G11C17/16

CPC分类号： G11C29/785 ,  H01L23/5256 ,  H01L27/1126 ,  H01L2924/0002

摘要： There is disclosed an improved semiconductor memory device having a regular memory cell array and a spare memory cell array. Each spare memory cell constituting the spare memory cell array includes a first transistor selected by a read word line, whose drain is connected to a spare bit line and source is connected via a fuse to a power supply, and a second transistor connected between the interconnection between the first transistor and fuse and a ground. The fuse is selectively blown by flowing a blowing current through the fuse by selecting the second transistor through a write line to thereby disconnect a discharge current path of the spare bit line. The threshold voltage of the second transistor of the spare memory cell which is made conductive upon selection by the write line when the blowing current flows through the fuse is higher than a potential difference between a potential generated at the write line connected with another spare memory cell and a ground potential. Such a high threshold voltage is obtained by including in manufacture of the memory cell the steps of implanting impurity ions of a first conductivity type to the channel area of a region on the surface of a semiconductor substrate where transistors including the second transistor of a second conductivity type different from the first conductivity type are formed; and implanting impurity ions of the one conductivity type to the channel area of the second transistor and to the channel area of transistors of a conductivity type different from the second transistor; whereby the impurity ions are implanted twice to the channel area of the second transistor.

公开(公告)号：US5138579A

公开(公告)日：1992-08-11

申请号：US632613

申请日：1990-12-26

申请人： Yuuichi Tatsumi ,  Hidenobu Minagawa ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

发明人： Yuuichi Tatsumi ,  Hidenobu Minagawa ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

IPC分类号： G11C7/00 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00

CPC分类号： G11C16/28

摘要： A semiconductor memory device includes word lines selectively driven by a signal from a row decoder, memory cells connected to word lines, first and second data lines, a bit line connected to receive data from the memory cell and to supply received data to the first data lines, dummy cells connected to word lines, first and second dummy data lines, a dummy bit lines connected to receive data from the dummy memory cell and to supply received data to the first dummy data line, a data sensing circuit for generating an output signal corresponding to a potential difference between the second data line and second dummy data line, a first MOS transistor connected between the first and second data lines, a first load circuit for charging the second data line, a second MOS transistor connected between the first and second dummy data lines, and a second load circuit for charging the second dummy data lines. The memory device further includes a first equalizer circuit connected between the second data line and dummy data line and equalizing potentials at both ends during a predetermined period of time after the semiconductor memory device is set in the active mode, and a second equalizer circuit connected between the data line and dummy data line and equalizing potential as at both ends during a predetermined period of time after the memory device is set in the active mode.

摘要翻译： 半导体存储器件包括由来自行解码器的信号选择性地驱动的字线，连接到字线的存储器单元，第一和第二数据线，连接到从存储器单元接收数据并将接收到的数据提供给第一数据的位线 连接到字线的虚拟单元，第一和第二虚拟数据线，连接成从虚拟存储单元接收数据并将接收到的数据提供给第一虚拟数据线的虚拟位线;数据感测电路，用于产生输出信号 对应于第二数据线和第二虚拟数据线之间的电位差，连接在第一和第二数据线之间的第一MOS晶体管，用于对第二数据线充电的第一负载电路，连接在第一和第二数据线之间的第二MOS晶体管 虚拟数据线，以及用于对第二虚拟数据线进行充电的第二负载电路。 存储装置还包括连接在第二数据线和虚拟数据线之间的第一均衡器电路，并且在半导体存储器件被设置为激活模式之后的预定时间段期间使两端的电位相等，以及第二均衡器电路 数据线和虚拟数据线，并且在存储器件被设置为活动模式之后的预定时间段期间两端的均衡电位。

公开(公告)号：US5124948A

公开(公告)日：1992-06-23

申请号：US751574

申请日：1991-08-22

申请人： Makoto Takizawa ,  Taira Iwase ,  Masamichi Asano ,  Yasunori Arime

发明人： Makoto Takizawa ,  Taira Iwase ,  Masamichi Asano ,  Yasunori Arime

IPC分类号： G11C29/00

CPC分类号： G11C29/822

摘要： A main memory cell array is divided into a plurality of blocks, and a spare memory cell group is arranged apart from the main memory cell array. The spare memory cell group uses bit lines or word lines different from those of the main memory cell array and includes spare memory cells which are different in structure from the memory cells of the main memory cell array. The number of the memory cells of the spare memory cell group is the same as that of the main memory cells of one row or column in each block of the main memory cell array, and data can be programmed into the spare memory cells after the completion of the manufacturing process. The operation of programming data into the spare memory cells of the spare memory cell array is effected by use of a write-in address buffer and a write-in decoder. When a row or column including a defective memory cell is designated in the main memory cell array, the row or column of the spare memory cells in the spare memory cell group is activated.

摘要翻译： 主存储单元阵列被分成多个块，并且备用存储单元组被布置成与主存储单元阵列分开。 备用存储单元组使用与主存储单元阵列不同的位线或字线，并且包括与主存储单元阵列的存储单元结构不同的备用存储单元。 备用存储单元组的存储单元的数量与主存储单元阵列的每个块中的一个行或列的主存储单元的数量相同，并且可以在完成后将数据编程到备用存储单元中 的制造过程。 通过使用写入地址缓冲器和写入解码器来实现将数据编程到备用存储单元阵列的备用存储单元中的操作。 当在主存储单元阵列中指定包括有缺陷存储单元的行或列时，备用存储单元组中的备用存储单元的行或列被激活。

公开(公告)号：US5067111A

公开(公告)日：1991-11-19

申请号：US426803

申请日：1989-10-26

申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Sadayuki Yokoyama

发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Sadayuki Yokoyama

IPC分类号： G06F11/18 ,  G11C16/26

CPC分类号： G06F11/183 ,  G06F11/187 ,  G11C16/26

摘要： A semiconductor memory device comprising a first Electrically Erasable Programmable Read Only Memory (EEPROM) cell array, a first row decoder, a first column decoder, two second EEPROM arrays each having a storage area equal in capacity to the specified storage area defined in the first EEPROM array, a second row decoder, a second column decoder, and a majority logic circuit. The first row decoder and the first column decoder access one of the memory cells of the first EEPROM array. The second row decoder and the second column decoder access one of the memory cells of either the second EEPROM array when one of the memory cells of first EEPROM array is accessed. The majority logic circuit carries out a majority logic operation on the data items read from the accessed memory cell of the first EEPROM array and the data items read from the accessed memory cells of the second EEPROM arrays, thereby to determine which data item is to be read out to an external device.

摘要翻译： 一种半导体存储器件，包括第一电可擦除可编程只读存储器（EEPROM）单元阵列，第一行解码器，第一列解码器，两个第二EEPROM阵列，每个第二EEPROM阵列的容量等于在第一 EEPROM阵列，第二行解码器，第二列解码器和多数逻辑电路。 第一行解码器和第一列解码器访问第一EEPROM阵列的存储单元之一。 当访问第一EEPROM阵列的存储单元之一时，第二行解码器和第二列解码器访问第二EEPROM阵列中的一个存储器单元。 多数逻辑电路对从第一EEPROM阵列的访问存储单元读取的数据项和从第二EEPROM阵列的访问存储单元读取的数据项进行多数逻辑运算，从而确定哪个数据项将是 读出外部设备。

公开(公告)号：US4799195A

公开(公告)日：1989-01-17

申请号：US168560

申请日：1988-03-04

申请人： Hiroshi Iwahashi ,  Masamichi Asano

发明人： Hiroshi Iwahashi ,  Masamichi Asano

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  G11C29/00 ,  G11C29/12 ,  G11C11/40

CPC分类号： G11C16/28

摘要： A semiconductor memory device comprises memory cell transistors each having a double layered gate having a floating gate and a control gate. The memory device comprises a transistor for receiving a predetermined voltage from a source external to the memory device and providing it as a reference voltage in response to a control signal, and a sense amplifier for comparing a voltage dependent on the data read from the memory cell with the reference voltage.

摘要翻译： 半导体存储器件包括存储单元晶体管，每个存储单元晶体管具有一个具有浮置栅极和一个控制栅极的双层栅极。 存储器件包括晶体管，用于从存储器件外部的源接收预定电压并将其作为响应于控制信号的参考电压提供;以及读出放大器，用于根据从存储器单元读取的数据进行比较 具有参考电压。

公开(公告)号：US4725915A

公开(公告)日：1988-02-16

申请号：US717695

申请日：1985-03-29

申请人： Hiroshi Jwahashi ,  Masamichi Asano ,  Hiroshi Harada ,  Shinichi Tanaka ,  Hideki Sumihara

发明人： Hiroshi Jwahashi ,  Masamichi Asano ,  Hiroshi Harada ,  Shinichi Tanaka ,  Hideki Sumihara

IPC分类号： G11C16/10 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H03K3/353

CPC分类号： H01L27/0251 ,  G11C16/10 ,  H01L27/088

摘要： A semiconductor integrated circuit includes a MOS transistor, and a transistor circuit in which one end of a current path is connected to a drain of this MOS transistor and which has an avalanche breakdown voltage lower than a breakdown voltage of the MOS transistor.

摘要翻译： 半导体集成电路包括MOS晶体管和晶体管电路，其中电流路径的一端连接到该MOS晶体管的漏极，并且具有低于MOS晶体管的击穿电压的雪崩击穿电压。