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公开(公告)号：US4979146A
公开(公告)日：1990-12-18
申请号：US302712
申请日：1989-01-27
IPC分类号： G11C17/00 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/16 , H01L21/822 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/112 , H01L29/788 , H01L29/792
CPC分类号： G11C16/10 , G11C16/08 , G11C16/12 , G11C16/16 , H01L2924/0002
摘要： In an electrically erasable non-volatile semiconductor memory device, a plurality of non-volatile semiconductor memory cells are arranged in a matrix form and are connected to corresponding ones of row and column lines. In a data writing mode, a first voltage Vp at is applied to the column lines so that the drains of the memory cells are maintained at a drain potential, and a second voltage is applied to the row lines so that a sum level of the drain potential and the threshold voltage of the memory cell is not smaller than the floating gate potential of the memory cell.
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2.发明授权Semiconductor memory device having a majority logic for determining data to be read out 失效具有用于确定要读出的数据的多数逻辑的半导体存储器件
公开(公告)号：US5067111A
公开(公告)日：1991-11-19
申请号：US426803
申请日：1989-10-26
CPC分类号： G06F11/183 , G06F11/187 , G11C16/26
摘要： A semiconductor memory device comprising a first Electrically Erasable Programmable Read Only Memory (EEPROM) cell array, a first row decoder, a first column decoder, two second EEPROM arrays each having a storage area equal in capacity to the specified storage area defined in the first EEPROM array, a second row decoder, a second column decoder, and a majority logic circuit. The first row decoder and the first column decoder access one of the memory cells of the first EEPROM array. The second row decoder and the second column decoder access one of the memory cells of either the second EEPROM array when one of the memory cells of first EEPROM array is accessed. The majority logic circuit carries out a majority logic operation on the data items read from the accessed memory cell of the first EEPROM array and the data items read from the accessed memory cells of the second EEPROM arrays, thereby to determine which data item is to be read out to an external device.
摘要翻译： 一种半导体存储器件，包括第一电可擦除可编程只读存储器（EEPROM）单元阵列，第一行解码器，第一列解码器，两个第二EEPROM阵列，每个第二EEPROM阵列的容量等于在第一 EEPROM阵列，第二行解码器，第二列解码器和多数逻辑电路。 第一行解码器和第一列解码器访问第一EEPROM阵列的存储单元之一。 当访问第一EEPROM阵列的存储单元之一时，第二行解码器和第二列解码器访问第二EEPROM阵列中的一个存储器单元。 多数逻辑电路对从第一EEPROM阵列的访问存储单元读取的数据项和从第二EEPROM阵列的访问存储单元读取的数据项进行多数逻辑运算，从而确定哪个数据项将是 读出外部设备。
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公开(公告)号：US5034926A
公开(公告)日：1991-07-23
申请号：US392070
申请日：1989-08-10
摘要： In a non-volatile semiconductor memory of this invention, a memory cell array constituted by a plurality of memory cells is divided into a plurlaity of blocks, and erase lines which are common to the respective blocks and independent from each other are arranged. In the data write mode, a predetermined voltage is applied to only the erase line connected to a selected one of the blocks.
摘要翻译： 在本发明的非易失性半导体存储器中，由多个存储单元构成的存储单元阵列被划分为多个块，并且布置了各个块相互独立的擦除线。 在数据写入模式中，只将预定电压施加到连接到所选择的一个块的擦除线。
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公开(公告)号：US4916334A
公开(公告)日：1990-04-10
申请号：US226312
申请日：1988-07-29
摘要： A semiconductor integrated circuit includes a CMOS circuit operated on a voltage of a first voltage level to set an output node thereof to a voltage of the first voltage level or a reference voltage; an output circuit for controlling supply of a voltage of a second voltage level which is higher than the first voltage level to a signal output node; and an isolation MOS transistor having a current path connected between the output node of the CMOS circuit and the signal output node and a gate connected to receive a control signal. The output node of the CMOS circuit is set to the reference voltage with the conduction resistance of the isolation MOS transistor kept high after the lapse of period in which the voltage of the second voltage level is kept supplied to the signal output node. After this, the conduction resistance of the isolation MOS transistor is reduced in response to the control signal.
摘要翻译： 半导体集成电路包括以第一电压电平工作的CMOS电路，以将其输出节点设置为第一电压电平或参考电压的电压; 输出电路，用于控制向信号输出节点提供高于第一电压电平的第二电压电平的电压; 以及隔离MOS晶体管，其具有连接在CMOS电路的输出节点和信号输出节点之间的电流路径以及连接以接收控制信号的栅极。 CMOS电路的输出节点被设定为参考电压，其中隔离MOS晶体管的导通电阻保持高电平，其中第二电压电平的电压被保持提供给信号输出节点。 此后，隔离MOS晶体管的导通电阻响应于控制信号而减小。
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公开(公告)号：US4509148A
公开(公告)日：1985-04-02
申请号：US493605
申请日：1983-05-11
申请人： Masamichi Asano , Hiroshi Iwahashi
发明人： Masamichi Asano , Hiroshi Iwahashi
IPC分类号： G11C8/10 , G11C11/4076 , G11C11/408 , G11C17/12 , G11C11/40
CPC分类号： G11C17/12 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4085 , G11C11/4087 , G11C8/10
摘要： A semiconductor memory circuit includes a plurality of semiconductor memory areas, a plurality of data lines connected to the memory areas for the transfer of data with respect thereto, a plurality of word lines for transmitting access signals to the memory areas, a column decoder connected to the plurality of data lines and a row decoder having decoding sections respectively connected to the memory areas and switching MOS transistors connected between the decoder sections and a voltage supply terminal. The memory circuit further includes a memory selection circuit connected to the switching MOS transistors of said row decoders for controlling the conduction state of the switching MOS transistors.
摘要翻译： 半导体存储器电路包括多个半导体存储区域，连接到存储区域的多个数据线，用于相对于其传输数据;多条字线，用于将存取信号发送到存储区域;列解码器，连接到 所述多条数据线和行解码器具有分别连接到存储区域的解码部分和连接在解码器部分与电压供应端子之间的开关式MOS晶体管。 存储电路还包括连接到所述行解码器的开关MOS晶体管的存储器选择电路，用于控制开关MOS晶体管的导通状态。
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公开(公告)号：US4447895A
公开(公告)日：1984-05-08
申请号：US192203
申请日：1980-09-30
申请人： Masamichi Asano , Hiroshi Iwahashi
发明人： Masamichi Asano , Hiroshi Iwahashi
IPC分类号： G11C8/10 , G11C11/4076 , G11C11/408 , G11C17/12 , G11C11/40
CPC分类号： G11C17/12 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4085 , G11C11/4087 , G11C8/10
摘要： A semiconductor memory circuit includes a plurality of semiconductor memory areas, a plurality of data lines connected to the memory areas for the transfer of data with respect thereto, a plurality of word lines for transmitting access signals to the memory areas, a column decoder connected to the plurality of data lines and a row decoder having decoding sections respectively connected to the memory areas and switching MOS transistors connected between the decoder sections and a voltage supply terminal. The memory circuit further includes a memory selection circuit connected to the switching MOS transistors of the row decoders for controlling the conduction state of the switching MOS transistors.
摘要翻译： 半导体存储器电路包括多个半导体存储区域，连接到存储区域的多个数据线，用于相对于其传输数据;多条字线，用于将存取信号发送到存储区域;列解码器，连接到 所述多条数据线和行解码器具有分别连接到存储区域的解码部分和连接在解码器部分与电压供应端子之间的开关式MOS晶体管。 存储电路还包括连接到行解码器的开关MOS晶体管的存储器选择电路，用于控制开关MOS晶体管的导通状态。
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公开(公告)号：US5364805A
公开(公告)日：1994-11-15
申请号：US726881
申请日：1991-07-08
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/265
CPC分类号： H01L27/11517 , H01L27/115
摘要： A memory cell array is formed of a plurality of nonvolatile memory cell transistors arranged in a matrix form. The patterns of the control gate electrode and the source region of each memory cell transistor are formed in parallel and the pattern of the erasing gate electrode is formed to intersect the source region and control gate electrode patterns. A field oxide film is formed in an intersecting portion between the source region and the erasing gate electrode.
摘要翻译： 存储单元阵列由以矩阵形式布置的多个非易失性存储单元晶体管形成。 并联地形成每个存储单元晶体管的控制栅电极和源极区的图案，并且形成擦除栅电极的图案以与源区和控制栅电极图相交。 在源极区域和擦除栅极电极之间的交叉部分中形成场氧化膜。
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公开(公告)号：US5175704A
公开(公告)日：1992-12-29
申请号：US607468
申请日：1990-10-31
申请人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
发明人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
摘要： In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.
摘要翻译： 在非易失性半导体存储器件中，布线层连接在电源和存储单元之间。 布线层的电阻大于负载晶体管的导通电阻，负载晶体管基本上决定负载特性。 因此，载荷特性曲线在倾斜度上更为平缓，形状更为直线。 这使得数据写入操作对于形成存储单元的制造的晶体管的沟道长度的变化是稳定的。
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公开(公告)号：US4967394A
公开(公告)日：1990-10-30
申请号：US241748
申请日：1988-09-08
CPC分类号： G11C29/50012 , G11C16/08 , G11C16/28 , G11C16/32 , G11C16/34 , G11C29/24 , G11C29/50 , G11C29/52 , G11C16/04
摘要： A semiconductor memory device in which data can be read out in response to an address signal comprises power source lines, a plurality of row and column conductive lines, a memory cell array including nonvolatile memory cells arranged in a matrix form of rows and columns and respectively connected to the plurality of row and column lines and the power source lines, a first selector circuit for generating a signal for selecting the row conductive lines in response to an address signal, a dummy row line, and a dummy memory cells each having a source, a drain and a control gate connected to the dummy row line. In the semiconductor memory device, one of paths between the source and the power source line and between the drain and the corresponding row line is closed and the other path is opened, and it further includes a second selector circuit for selectively generating a line selection signal for selecting one of the row conductive lines in response to an address signal and a dummy selection signal for selecting the dummy row line in response to the same address signal.
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10.发明授权Semiconductor integrated circuit device having an object circuit to which output voltages of the sub- and main booster circuits are applied 失效半导体集成电路装置具有对主电路施加副主电路和主升压电路的输出电压的目标电路
公开(公告)号：US4905314A
公开(公告)日：1990-02-27
申请号：US184580
申请日：1988-04-21
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/088 , H01L27/10 , H01L29/788 , H01L29/792 , H02M3/07 , H03K3/356 , H03K17/06
CPC分类号： G11C5/145 , G11C16/30 , H03K17/06 , H03K3/356008
摘要： A sub-booster circuit for further stepping up an output voltage of a main booster circuit includes a first MOS transistor having a drain connected to the output terminal of the main booster circuit, and a gate connected to an input terminal of an object circuit, a second MOS transistor having a drain and a gate connected to the source of the first MOS transistor and a source connected to the input terminal of the object circuit, and a MOS capacitor having a first electrode connected to a connection node between the first and second MOS transistors and a second electrode connected to receive a clock pulse signal. A threshold voltage of the second MOS transistor is set to be larger in its absolute value than a threshold voltage of the first MOS transistor and the MOS capacitor has substantially the same threshold voltage as that of the second MOS transistor.
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