公开(公告)号：US5610858A

公开(公告)日：1997-03-11

申请号：US440471

申请日：1995-05-12

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0433 ,  G11C16/0491

摘要： Memory cells, each formed of an EEPROM, are series-connected with transistors. Blocks, each of which is constructed by one memory cell and one transistor connected in series, are arranged in a matrix form. The memory cell and transistor of each block are controlled by different row lines. The memory cell and transistor of each block are connected to different column lines, and the column line connected to the memory cell of one of the adjacent blocks which are controlled by the same row line is connected to the transistor of the other block.

摘要翻译： 每个由EEPROM构成的存储单元与晶体管串联连接。 每个由一个存储单元和一个串联连接的晶体管构成的块以矩阵形式布置。 每个块的存储单元和晶体管由不同的行线控制。 每个块的存储单元和晶体管连接到不同的列线，并且连接到由相同行线控制的相邻块之一的存储单元的列线连接到另一块的晶体管。

公开(公告)号：US5579260A

公开(公告)日：1996-11-26

申请号：US296747

申请日：1994-08-26

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of "0" or "1" of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

公开(公告)号：US5519660A

公开(公告)日：1996-05-21

申请号：US235376

申请日：1994-04-29

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C17/00 ,  G11C7/12 ,  G11C16/06 ,  G11C16/24 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C16/24

摘要： There is disclosed a semiconductor memory device which can decrease precharge current and stably read out data, e.g., EEPROM, etc., having column line potential setting transistors connected between precharging transistors and their corresponding column lines. The column line potential setting transistor maintains precharging potential of the column line to a low value for suppressing instantaneous current by precharging to a low value and in a read cycle after precharge it further lowers the gate potential applied to the gate of the column line potential setting transistors to a value lower than a potential of the gate for the precharge period thereby prevent an erroneous operation by the capacitive coupling between column lines.

摘要翻译： 公开了一种半导体存储器件，其可以降低预充电电流并稳定地读出数据，例如具有连接在预充电晶体管与其相应的列线之间的列线电位设置晶体管的EEPROM等。 列线电位设定晶体管将列线的预充电电位保持为低电平，以通过预充电至低电压来抑制瞬时电流，并且在预充电之后的读取周期中进一步降低施加到栅极电位设置的栅极的栅极电位 晶体管的值低于预充电时段的栅极电位，从而防止列线之间电容耦合的错误操作。

公开(公告)号：US5508957A

公开(公告)日：1996-04-16

申请号：US312072

申请日：1994-09-26

申请人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/115 ,  G11C16/06 ,  H01L29/788

CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H01L27/115

摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管 晶体管和地。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。 在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压 将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元 。 用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

公开(公告)号：US5270969A

公开(公告)日：1993-12-14

申请号：US913451

申请日：1992-07-15

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C11/40

CPC分类号： G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

摘要： The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuits. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

摘要翻译： 多个浮栅型MOSFET的电流路径串联连接形成串联电路。 串联电路在一端连接以接收参考电压，并连接到数据编程和读出电路。 在数据编程模式下，电子从浮置栅极放电到MOSFET的漏极，或者将漏极注入到浮动栅极中。 数据读出操作通过检查电流是否从串联电路的另一端流向一端来实现。

公开(公告)号：US4635232A

公开(公告)日：1987-01-06

申请号：US477880

申请日：1983-03-23

申请人： Hiroshi Iwahashi ,  Fujio Masuoka

发明人： Hiroshi Iwahashi ,  Fujio Masuoka

IPC分类号： G11C17/00 ,  G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40

CPC分类号： G11C29/785 ,  G11C29/83

摘要： A semiconductor memory device is disclosed, which comprises a main memory, a decoder for selecting the main memory, an auxiliary memory, transistors connected between the auxiliary memory and the decoder for selecting the auxiliary memory according to the output of the decoder, and circuits for controlling the transistors. The transistors render the main memory inoperative when the auxiliary memory is rendered operative.

摘要翻译： 公开了一种半导体存储器件，其包括主存储器，用于选择主存储器的解码器，辅助存储器，连接在辅助存储器和解码器之间的晶体管，用于根据解码器的输出选择辅助存储器，以及用于 控制晶体管。 当辅助存储器可操作时，晶体管使主存储器不起作用。

公开(公告)号：US07064979B2

公开(公告)日：2006-06-20

申请号：US10897084

申请日：2004-07-21

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C16/04

CPC分类号： G11C16/24 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/26

摘要： In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored such in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the date latch circuits can be formed at any positions remote from the memory cell array.

摘要翻译： 在非易失性半导体存储器中，在读取期间可以通过存储单元流过大电流。 可以减少列线的数量。 对各个存储单元的浮置栅极的电子注入被平均以减小其阈值电压的偏差。 来自相应存储单元的浮置栅极的电子发射也被平均以减小其阈值电压的偏差。 可以防止由于锁存电路引起的芯片尺寸的增加。 通过注意到二进制数据的多个“0”或“1”中的任一个存储在存储单元组或块的存储单元中，负阈值电压被分配给用于存储更多位侧的存储单元 二进制数据的数据。 对于两个相邻的存储器块，共同使用单列线。 为了将电子注入存储单元的浮动栅极，电压逐渐增加并且当电子注入到预定的注入速率时停止。 电子一次从浮动栅极发射，此后再次注入电子以存储二进制数据之一。 此外，日期锁存电路可以形成在远离存储单元阵列的任何位置处。

公开(公告)号：US06344999B1

公开(公告)日：2002-02-05

申请号：US09677902

申请日：2000-10-03

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C1604

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

摘要翻译： 在非易失性半导体存储器中，在读取期间可以通过存储单元流过大电流。 可以减少列线的数量。 对各个存储单元的浮置栅极的电子注入被平均以减小其阈值电压的偏差。 来自相应存储单元的浮置栅极的电子发射也被平均以减小其阈值电压的偏差。 可以防止由于锁存电路引起的芯片尺寸的增加。 通过注意到二进制数据的多个“0”或“1”中的任何一个存储在存储器单元组或块的存储单元中，将负阈值电压分配给用于存储更多位侧的存储单元 二进制数据的数据。 对于两个相邻的存储器块，共同使用单列线。 为了将电子注入存储单元的浮动栅极，电压逐渐增加并且当电子注入到预定的注入速率时停止。 电子一次从浮动栅极发射，此后再次注入电子以存储二进制数据之一。 此外，数据锁存电路可以形成在远离存储单元阵列的任何位置处。

公开(公告)号：US06292423B1

公开(公告)日：2001-09-18

申请号：US09605423

申请日：2000-06-28

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C700

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/08 ,  G11C2211/5642

摘要： A nonvolatile semiconductor memory is disclosed. This nonvolatile semiconductor memory includes a memory cell string containing a selection transistor and at least one cell transistor which is connected to the selection transistor and has a floating gate. This memory further includes a bias circuit for, when the selection transistor is unselected, supplying a potential different from the ground potential to the gate of the cell transistor connected to the unselected selection transistor.

摘要翻译： 公开了一种非易失性半导体存储器。 该非易失性半导体存储器包括一个包含选择晶体管的存储单元串和至少一个与选择晶体管相连并具有浮置栅极的单元晶体管。 该存储器还包括偏置电路，用于当选择晶体管未被选择时，向与未选择的选择晶体管连接的单元晶体管的栅极提供不同于地电位的电位。

公开(公告)号：US6072748A

公开(公告)日：2000-06-06

申请号：US305479

申请日：1999-05-06

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C8/00

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

摘要： The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.