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    Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through
    1.
    发明授权
    Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through 失效
    具有NAND单元结构的非易失性半导体存储器和具有不同通道长度的开关晶体管以减少穿通

    公开(公告)号：US5508957A

    公开(公告)日：1996-04-16

    申请号：US312072

    申请日：1994-09-26

    申请人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

    发明人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

    IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/115 ,  G11C16/06 ,  H01L29/788

    CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H01L27/115

    摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

    摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管 晶体管和地。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。 在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压 将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元 。 用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

    Process for forming arrayed field effect transistors highly integrated on substrate
    2.
    发明授权
    Process for forming arrayed field effect transistors highly integrated on substrate 失效
    用于形成高度集成在衬底上的阵列场效应晶体管的工艺

    公开(公告)号：US5397723A

    公开(公告)日：1995-03-14

    申请号：US728585

    申请日：1991-07-11

    申请人： Riichiro Shirota ,  Masaki Momodomi ,  Ryozo Nakayama ,  Seiichi Aritome ,  Ryouhei Kirisawa ,  Tetsuro Endoh ,  Shigeyoshi Watanabe

    发明人： Riichiro Shirota ,  Masaki Momodomi ,  Ryozo Nakayama ,  Seiichi Aritome ,  Ryouhei Kirisawa ,  Tetsuro Endoh ,  Shigeyoshi Watanabe

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265 ,  H01L21/465

    CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11517

    摘要： A process for forming an array of FATMOS transistors serving as memory cells of a NAND cell type EEPROM. A multi-layered structure is provided on a substrate with two stacked conductive layers insulated by an intermediate insulative layer, the first or inner conductive layer being insulated by a first insulative layer from the substrate, the second or outer conductive layer being covered with a second insulative layer. The second insulative layer is etched to define a first array of etched layer portions. A photoresist layer is deposited and etched to define a second array of layer portions, each of which is positioned between two neighboring ones of the first array of layer portions. The multi-layered structure is etched with the first and second layer portions being as a mask, to thereby form an array of a plurality of pairs of insulated gate electrodes above the substrate. A chosen impurity is doped into the substrate with the insulated gate electrodes serving as a mask to thereby form impurity-doped regions in the substrate.

    摘要翻译： 用于形成用作NAND单元型EEPROM的存储单元的FATMOS晶体管阵列的工艺。 多层结构设置在具有由中间绝缘层绝缘的两个层叠导电层的基板上，第一或内部导电层由与基板隔开的第一绝缘层，第二或外部导电层被第二 绝缘层。 蚀刻第二绝缘层以限定蚀刻层部分的第一阵列。 沉积和蚀刻光致抗蚀剂层以限定层部分的第二阵列，每个层部分位于层部分的第一阵列中的两个相邻的层部分之间。 用第一和第二层部分作为掩模蚀刻多层结构，从而在衬底上形成多对绝缘栅电极的阵列。 将所选择的杂质掺杂到衬底中，其中绝缘栅电极用作掩模，从而在衬底中形成杂质掺杂区域。

    Electrically erasable programmable read-only memory with NAND memory cell structure
    3.
    发明授权
    Electrically erasable programmable read-only memory with NAND memory cell structure 失效
    具有NAND存储单元结构的电可擦除可编程只读存储器

    公开(公告)号：US4996669A

    公开(公告)日：1991-02-26

    申请号：US489967

    申请日：1990-03-07

    申请人： Tetsuo Endoh ,  Riichiro Shirota ,  Masaki Momodomi ,  Tomoharu Tanaka ,  Fujio Masuoka ,  Shigeyoshi Watanabe

    发明人： Tetsuo Endoh ,  Riichiro Shirota ,  Masaki Momodomi ,  Tomoharu Tanaka ,  Fujio Masuoka ,  Shigeyoshi Watanabe

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483

    摘要： An electrically erasable programmable read-only memory with a NAND cell structure has parallel bit lines, and memory cells defining NAND cell blocks, each of which has a series-circuit of memory cell transistors. Each transistor has a floating gate and a control gate. Parallel word lines are connected to the control gates of the cell transistors. The first, second and third intermediate voltages are used in the data write mode: the first voltage is lower than the "H" level voltage and higher than the "L" level voltage; the second and third voltages are higher than the first voltage and lower than the "H" level voltage. Data is written into a selected memory cell transistor of a NAND cell block, by applying the "H" level voltage to a word line connected to the selected transistor, applying the second voltage to the remaining unselected word lines, applying a corresponding bit line associated with the selected transistor with one of the first and third voltages which is selected in accordance with a logic level of the data, and applying unselected bit lines with the third voltage, whereby carriers are moved by tunneling from or to the floating gate of the selected memory cell transistor.

    摘要翻译： 具有NAND单元结构的电可擦除可编程只读存储器具有并行位线，以及限定NAND单元块的存储器单元，每个存储单元具有存储单元晶体管的串联电路。 每个晶体管都有一个浮动栅极和一个控制栅极。 并行字线连接到单元晶体管的控制栅极。 在数据写入模式下使用第一，第二和第三中间电压：第一电压低于“H”电平电压并高于“L”电平电压; 第二和第三电压高于第一电压并低于“H”电平电压。 将数据写入NAND单元块的选定的存储单元晶体管中，通过将“H”电平电压施加到连接到所选晶体管的字线，将第二电压施加到剩余的未选字线，施加相应的位线 其中所选择的晶体管具有根据数据的逻辑电平选择的第一和第三电压中的一个，以及施加具有第三电压的未选择的位线，由此通过隧道从所选择的浮动栅极或者所选择的浮动栅极 存储单元晶体管。

    Electrically erasable programmable read-only memory with NAND memory cell structure
    4.
    发明授权
    Electrically erasable programmable read-only memory with NAND memory cell structure 失效
    具有NAND存储单元结构的电可擦除可编程只读存储器

    公开(公告)号：US5088060A

    公开(公告)日：1992-02-11

    申请号：US634325

    申请日：1990-12-26

    申请人： Tetsuo Endoh ,  Riichiro Shirota ,  Masaki Momodomi ,  Tomoharu Tanaka ,  Fujio Masuoka ,  Shigeyoshi Watanabe

    发明人： Tetsuo Endoh ,  Riichiro Shirota ,  Masaki Momodomi ,  Tomoharu Tanaka ,  Fujio Masuoka ,  Shigeyoshi Watanabe

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483

    摘要： An electrically erasable programmable read-only memory with a NAND cell structure has parallel bit lines, and memory cells defining NAND cell blocks, each of which has a series-circuit of memory cell transistors. Each transistor has a floating gate and a control gate. Parallel word lines are connected to the control gates of the cell transistors. The first, second and third intermediate voltages are used in the data write mode: the first voltage is lower than the "H" level voltage and higher than the "L" level voltage; the second and third voltages are higher than the first voltage and lower than the "H" level voltage. Data is written into a selected memory cell transistor of a NAND cell block, by applying the "H" level voltage to a word line connected to the selected transistor, applying the second voltage to the remaining unselected word lines, applying a corresponding bit line associated with the selected transistor with one of the first and third voltages which is selected in accordance with a logic level of the data, and applying unselected bit lines with the third voltage, whereby carriers are moved by tunneling from or to the floating gate of the selected memory cell transistor.

    摘要翻译： 具有NAND单元结构的电可擦除可编程只读存储器具有并行位线，以及限定NAND单元块的存储器单元，每个存储单元具有存储单元晶体管的串联电路。 每个晶体管都有一个浮动栅极和一个控制栅极。 并行字线连接到单元晶体管的控制栅极。 在数据写入模式下使用第一，第二和第三中间电压：第一电压低于“H”电平电压并高于“L”电平电压; 第二和第三电压高于第一电压并低于“H”电平电压。 将数据写入NAND单元块的选定的存储单元晶体管中，通过将“H”电平电压施加到连接到所选晶体管的字线，将第二电压施加到剩余的未选字线，施加相应的位线 其中所选择的晶体管具有根据数据的逻辑电平选择的第一和第三电压中的一个，以及施加具有第三电压的未选择的位线，由此通过隧道从所选择的浮动栅极或者所选择的浮动栅极 存储单元晶体管。

    Semiconductor memory system with dynamic random access memory cells
    5.
    发明授权
    Semiconductor memory system with dynamic random access memory cells 失效
    具有动态随机存取存储单元的半导体存储器系统

    公开(公告)号：US4800530A

    公开(公告)日：1989-01-24

    申请号：US85086

    申请日：1987-08-13

    申请人： Yasuo Itoh ,  Fumio Horiguchi ,  Shigeyoshi Watanabe ,  Kazunori Ohuchi ,  Mitsugi Ogura

    发明人： Yasuo Itoh ,  Fumio Horiguchi ,  Shigeyoshi Watanabe ,  Kazunori Ohuchi ,  Mitsugi Ogura

    IPC分类号： G11C11/40 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22

    CPC分类号： G11C7/22 ,  G11C7/00 ,  G11C7/1033

    摘要： A dynamic random access memory system comprises first and second memory banks. A plurality of memory cells connected to a word line are grouped into first and second groups. The first group is arranged in the first memory bank and the second group is arranged in the second memory bank. Read/write means is provided in which each n bits from and to the first group and each n bits from and to the second group are read and written alternatively. Each bit is read and written in synchronism with the toggles of a column address strobe signal.

    摘要翻译： 动态随机存取存储器系统包括第一和第二存储体。 连接到字线的多个存储单元被分组为第一组和第二组。 第一组布置在第一存储体中，第二组布置在第二存储体中。 提供读/写装置，其中从第一组的每个n位和从第二组的每个n位和第二组的每个n位被交替地读取和写入。 每个位与列地址选通信号的切换同步读写。

    Semiconductor memory device having register groups for writing and reading data
    8.
    发明授权
    Semiconductor memory device having register groups for writing and reading data 失效
    具有用于写入和读取数据的寄存器组的半导体存储器件

    公开(公告)号：US5467303A

    公开(公告)日：1995-11-14

    申请号：US380443

    申请日：1995-01-30

    申请人： Takehiro Hasegawa ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    发明人： Takehiro Hasegawa ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    IPC分类号： G11C11/405 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4096 ,  G11C11/24 ,  G11C7/00

    CPC分类号： G11C11/4096 ,  G11C11/404

    摘要： A semiconductor memory device comprises an array of memory cell units, each of which has a plurality of MOS transistors connected in series and a plurality of information storage capacitors corresponding in number to the MOS transistors and each having its one end connected to the source of a corresponding one of the MOS transistors, and a plurality of register groups each of which is adapted to temporarily store information stored in one of the memory cell units for each column of the array in order to read from and write into each memory cell unit.

    摘要翻译： 半导体存储器件包括一组存储单元单元，每个存储单元单元具有串联连接的多个MOS晶体管和多个与MOS晶体管相对应的多个信息存储电容器，每个信号存储电容器的一端连接到 对应的一个MOS晶体管，以及多个寄存器组，每个寄存器组适于临时存储存储在阵列的每列的存储单元单元之一中的信息，以便从每个存储单元单元读取和写入。

    Dynamic random access memory device
    10.
    发明授权
    Dynamic random access memory device 失效
    动态随机存取存储器

    公开(公告)号：US06295241B1

    公开(公告)日：2001-09-25

    申请号：US08251649

    申请日：1994-05-31

    申请人： Shigeyoshi Watanabe ,  Tsuneaki Fuse ,  Koji Sakui ,  Masako Ohta ,  Yukihito Oowaki ,  Kenji Numata ,  Fujio Masuoka

    发明人： Shigeyoshi Watanabe ,  Tsuneaki Fuse ,  Koji Sakui ,  Masako Ohta ,  Yukihito Oowaki ,  Kenji Numata ,  Fujio Masuoka

    IPC分类号： G11C702

    CPC分类号： G11C11/4091 ,  G11C7/062 ,  G11C7/14 ,  G11C11/4099

    摘要： Here is disclosed a dynamic semiconductor memory of high integration density, which has parallel word lines and parallel bit lines formed on a substrate. The bit lines include a pair of bit lines. A memory cell is coupled to a word line and to one bit line of the bit-line pair. The memory cell is composed of MOSFETs of a submicron size. A sense amplifier section is connected to the pair of bit lines, and senses and amplifies the potential difference between the pair of bit lines in a data readout mode. The amplifier section has a BIMOS structure, having MOSFETs and bipolar transistors. It has a driver section comprised of bipolar transistors.

    摘要翻译： 这里公开了具有高集成度密度的动态半导体存储器，其具有在基板上形成的并行字线和并行位线。 位线包括一对位线。 存储器单元耦合到字线和位线对的一个位线。 存储单元由亚微米尺寸的MOSFET组成。 读出放大器部分连接到一对位线，并且在数据读出模式下感测和放大一对位线之间的电位差。 放大器部分具有BIMOS结构，具有MOSFET和双极晶体管。 它具有由双极晶体管组成的驱动器部分。