公开(公告)号：US10943792B2

公开(公告)日：2021-03-09

申请号：US16325665

申请日：2016-09-27

Applicant: Intel Corporation ,  Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Howe Yin Loo

Inventor： Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Howe Yin Loo

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/48 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L29/06 ,  H01L23/00 ,  H01L25/18

Abstract: A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.

公开(公告)号：US10856454B2

公开(公告)日：2020-12-01

申请号：US16535766

申请日：2019-08-08

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Yew San Lim ,  Jia Yan Go ,  Tin Poay Chuah ,  Eng Huat Goh

IPC: H05K9/00 ,  H05K3/46 ,  H05K1/11

Abstract: Apparatus and method for providing an electromagnetic interference (EMI) shield for removable engagement with a printed circuit board (PCB). A shaped electrically conductive member has a substantially planar member portion with multiple lateral member edges. The sidewalls are disposed at respective lateral member edges and are substantially orthogonal to the substantially planar member portion. At least one of the sidewalls includes at least one first snap-fit latching feature to engage a respective complementary second snap-fit latching feature disposed at one or more of multiple peripheral portions of a PCB.

公开(公告)号：US10716209B2

公开(公告)日：2020-07-14

申请号：US16565639

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Eng Huat Goh ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim

IPC: H05K1/11 ,  H05K3/40 ,  H05K1/03 ,  H05K3/46

Abstract: To overcome the problem of the fiber weave effect desynchronizing differential signals in a pair of traces of approximately the same length in a printed circuit board, the pair of traces can be routed to traverse largely parallel paths that are above one another in the printed circuit board. The material between the paths can include weaved fiber bundles. The material on opposite sides of the paths, surrounding the pair of traces and the weaved fiber bundles, can include resin-rich material. As a result, the pair of traces are directly adjacent to the same materials, which can allow signals in the traces to propagate at the same speed, and prevent desynchronization of differential signals traversing the paths. The path length difference associated with traversing to different depths can be compensated with a relatively small in-plane diagonal jog of one of the traces.

公开(公告)号：US20190221529A1

公开(公告)日：2019-07-18

申请号：US15869992

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Khang Choong Yong ,  Boon Ping Koh ,  Eng Huat Goh ,  Min Suet Lim ,  Wil Choon Song

IPC: H01L23/66 ,  H01L23/552 ,  H01L23/24 ,  H01L21/48 ,  H01L25/18 ,  H01Q1/52 ,  H01Q1/22

CPC classification number: H01L23/66 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/24 ,  H01L23/552 ,  H01L23/562 ,  H01L25/18 ,  H01L2223/6677 ,  H01Q1/2283 ,  H01Q1/44 ,  H01Q1/526 ,  H01Q7/00 ,  H04B15/02

Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a transmitter, a receiver, and a package stiffening element. The package stiffening element may be in electrical communication with the transmitter and the receiver. The package stiffening element may be configured to act as an antenna for both the transmitter and the receiver.

公开(公告)号：US20190103357A1

公开(公告)日：2019-04-04

申请号：US15720393

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Eng Huat Goh ,  Khang Choong Yong ,  Wil Choon Song ,  Jiun Hann Sir ,  Boon Ping Koh

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  B81C1/00 ,  H01L23/48 ,  H01L23/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first package, wherein the first package includes a first substrate section and a second substrate section. A plurality of stacked die may be disposed between the first substrate section and the second substrate section, wherein a surface of a first die of the plurality of stacked die is coplanar with a surface of the first section and with a surface of the second section. A second package is physically and electrically coupled to the first package.

公开(公告)号：US20190093402A1

公开(公告)日：2019-03-28

申请号：US16012469

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Poh Tat Oh

IPC: E05D3/06 ,  H05K5/02 ,  E05D11/00 ,  G06F1/16 ,  G06F1/32

Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.

公开(公告)号：US20190050040A1

公开(公告)日：2019-02-14

申请号：US16146463

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Rajashree Baskaran ,  Maruti Gupta Hyde ,  Min Suet Lim ,  Van Le ,  Hebatallah Saadeldeen

IPC: G06F1/32

Abstract: Methods and apparatus to provide power management for multi-die stacks using artificial intelligence are disclosed. An example multi-die package includes a computer processor unit (CPU) die, a memory die stacked in vertical alignment with the CPU die, and artificial intelligence (AI) architecture circuitry to infer a workload for at least one of the CPU die or the memory die. The AI architecture circuitry is to manage power consumption of at least one of the CPU die or the memory die based on the inferred workload.

公开(公告)号：US20190008052A1

公开(公告)日：2019-01-03

申请号：US16003970

申请日：2018-06-08

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Tin Poay Chuah ,  Han Kung Chua

IPC: H05K3/46 ,  H05K1/02 ,  H05K1/18 ,  H05K3/30

Abstract: Disclosed herein is a multi-planar circuit board, as well as related structures and methods. In an embodiment, a circuit board may include a first surface, a first section having the first surface in a first plane, a second section having the first surface in a second plane, and a third section connecting the first and second sections, where the third section defines a gradient between the first and second planes, and where all sections are sections within a contiguous board. In another embodiment, circuit board may further include a first component having a first thickness coupled on the first face of the first section, and a second component having a second thickness, greater than the first component, coupled on the first face of the second section, where the second section is in a lower plane, and where the overall thickness is the circuit board thickness plus the second thickness.

公开(公告)号：US10041282B2

公开(公告)日：2018-08-07

申请号：US14998225

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Chung Peng Jackson Kong ,  Poh Tat Oh

IPC: E05D3/06 ,  G06F1/16 ,  G06F1/32 ,  E05D11/00 ,  H05K5/02

Abstract: A personal computing device is provided with a first housing portion, a second housing portion, and a hinge joining the first housing portion to the second housing portion. The hinge is configured to allow the first housing portion to rotate substantially three-hundred-sixty degrees relative to the second housing portion. The hinge can be implemented as a plurality of interlinked parallel hinge segments, each hinge segment to rotate about a respective one of a plurality of parallel axes of the hinge to enable the rotation of the first housing portion.

公开(公告)号：US20180175002A1

公开(公告)日：2018-06-21

申请号：US15380669

申请日：2016-12-15

Applicant: Intel Corporation

Inventor： Howe Yin Loo ,  Eng Huat Goh ,  Min Suet Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652

Abstract: A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a package bottom interposer disposed on the package substrate on a land side. A land side board mates with the package bottom interposer, and enough vertical space is created by the package bottom interposer to allow space for at least one device disposed on the package substrate on the land side.