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公开(公告)号：US11158731B2
公开(公告)日：2021-10-26
申请号：US16642886
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： Ravi Pillarisetty , Van H. Le , Nicole K. Thomas , Hubert C. George , Jeanette Roberts , Payam Amin , Zachary R. Yoscovits , Roman Caudillo , James S. Clarke , Roza Kotlyar , Kanwaljit Singh
IPC: H01L29/66 , G06N10/00 , H01L21/8234 , H01L27/088 , H01L27/12 , H01L29/15 , H01L29/78 , H01L29/82 , H01L29/43
Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.
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公开(公告)号：US20200350423A1
公开(公告)日：2020-11-05
申请号：US16642886
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： Ravi Pillarisetty , Van H. Le , Nicole K. Thomas , Hubert C. George , Jeanette Roberts , Payam Amin , Zachary R. Yoscovits , Roman Caudillo , James S. Clarke , Roza Kotlyar , Kanwaljit Singh
IPC: H01L29/66 , H01L29/82 , H01L29/78 , H01L27/088 , H01L27/12 , H01L21/8234 , H01L29/15 , G06N10/00
Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.
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公开(公告)号：US20200321436A1
公开(公告)日：2020-10-08
申请号：US16650299
申请日：2017-12-23
Applicant: Intel Corporation
Inventor： Ravi Pillarisetty , Hubert C. George , Nicole K. Thomas , Jeanette M. Roberts , Roman Caudillo , Zachary R. Yoscovits , Kanwaljit Singh , Roza Kotlyar , Patrick H. Keys , James S. Clarke
Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.
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公开(公告)号：US10565515B2
公开(公告)日：2020-02-18
申请号：US16013384
申请日：2018-06-20
Applicant: Intel Corporation
Inventor： Lester Lampert , Ravi Pillarisetty , Nicole K. Thomas , Hubert C. George , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Zachary R. Yoscovits , James S. Clarke
Abstract: Embodiments of the present disclosure describe quantum circuit assemblies utilizing triaxial cables to communicate signals to/from quantum circuit components. One assembly includes a cooling apparatus for cooling a quantum circuit component that includes at least one qubit device. The cooling apparatus includes at least one triaxial connector for providing signals to and/or receiving signals from the quantum circuit component using one or more triaxial cables. Other assemblies include quantum circuit components and various electronic components (e.g. attenuators, filters, or amplifiers) for use within the cooling apparatus, adapted to be used with triaxial cables by incorporating triaxial connectors as well.
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公开(公告)号：US10475912B2
公开(公告)日：2019-11-12
申请号：US15900655
申请日：2018-02-20
Applicant: Intel Corporation
Inventor： Nicole K. Thomas , Ravi Pillarisetty , Kanwaljit Singh , Hubert C. George , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Zachary R. Yoscovits , Lester Lampert , James S. Clarke , Willy Rachmady
Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.
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Patent Agency Ranking
公开(公告)号：US10468578B2
公开(公告)日：2019-11-05
申请号：US15899918
申请日：2018-02-20
Applicant: Intel Corporation
Inventor： Adel A. Elsherbini , Javier A. Falcon , Roman Caudillo , James S. Clarke
Abstract: An exemplary superconducting qubit device package includes a qubit die housing a superconducting qubit device that includes at least one resonator, and a package substrate, each having a first face and an opposing second face. The resonator is disposed on the first face of the qubit die. The first face of the qubit die faces and is attached to the second face of the package substrate by first level interconnects. The second face of the package substrate includes a superconductor facing at least portions of the resonator. Such a package architecture may advantageously allow reducing design complexity and undesired coupling, enable inclusion of larger numbers of qubit devices in the qubit die of the package, reduce potential negative impact of the materials used in the package substrate on resonator performance, and limit some sources of qubit decoherence.
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公开(公告)号：US10388848B2
公开(公告)日：2019-08-20
申请号：US15924410
申请日：2018-03-19
Applicant: Intel Corporation
Inventor： Nicole K. Thomas , James S. Clarke , Jessica M. Torres , Lester Lampert , Ravi Pillarisetty , Hubert C. George , Kanwaljit Singh , Jeanette M. Roberts , Roman Caudillo , Zachary R. Yoscovits , David J. Michalak
Abstract: Embodiments of the present disclosure describe use of isotopically purified materials in donor- or acceptor-based spin qubit devices and assemblies. An exemplary spin qubit device assembly may include a semiconductor host layer that includes an isotopically purified material, a dopant atom in the semiconductor host layer, and a gate proximate to the dopant atom. An isotopically purified material may include a lower atomic-percent of isotopes with nonzero nuclear spin than the natural abundance of those isotopies in the non-isotopically purified material. Reducing the presence of isotopes with nonzero nuclear spin in a semiconductor host layer may improve qubit coherence and thus performance of spin qubit devices and assemblies.
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公开(公告)号：US10347834B2
公开(公告)日：2019-07-09
申请号：US15928220
申请日：2018-03-22
Applicant: INTEL CORPORATION
Inventor： Nicole K. Thomas , Marko Radosavljevic , Sansaptak Dasgupta , Ravi Pillarisetty , Kanwaljit Singh , Hubert C. George , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Zachary R. Yoscovits , Lester Lampert , James S. Clarke
Abstract: Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.
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公开(公告)号：US20190044066A1
公开(公告)日：2019-02-07
申请号：US15928220
申请日：2018-03-22
Applicant: INTEL CORPORATION
Inventor： Nicole K. Thomas , Marko Radosavljevic , Sansaptak Dasgupta , Ravi Pillarisetty , Kanwaljit Singh , Hubert C. George , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Zachary R. Yoscovits , Lester Lampert , James S. Clarke
CPC classification number: H01L49/006 , B82Y10/00 , B82Y20/00 , B82Y40/00 , G02B6/12004 , G02B2006/12078 , G02B2006/12142 , G06N10/00 , Y10S977/814 , Y10S977/933
Abstract: Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.
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公开(公告)号：US20190044049A1
公开(公告)日：2019-02-07
申请号：US15900674
申请日：2018-02-20
Applicant: Intel Corporation
Inventor： Nicole K. Thomas , Ravi Pillarisetty , Hubert C. George , Kanwaljit Singh , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Zachary R. Yoscovits , Lester Lampert , James S. Clarke , Willy Rachmady
Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.
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