公开(公告)号：US09395961B1

公开(公告)日：2016-07-19

申请号：US14960534

申请日：2015-12-07

Applicant: International Business Machines Corporation

Inventor： Jonathan D. Bradbury ,  Giles R. Frazier ,  Michael Karl Gschwind ,  Christian Jacobi ,  Anthony Saporito ,  Chung-Lung K. Shum

IPC: G06F9/45 ,  G06F9/44

CPC classification number: G06F9/44521

Abstract: Embodiments relate to fingerprint-based code version selection. An aspect includes based on a call to a method being issued by calling software that is currently executing on a processor of a computer system, determining a fingerprint comprising a representation of a sequence of behavior that occurs in the processor while the calling software is executing. Another aspect includes, based on determining that the match for the fingerprint is located in the entry in the fingerprint table, executing the associated code version of the method. Another aspect includes, based on determining that no match for the fingerprint is located in any entry in the fingerprint table: determining a new code version of the method by a compiler of the computer system; storing the fingerprint with an identifier of the new code version in a new entry in the fingerprint table; and executing the new code version.

Abstract translation: 实施例涉及基于指纹的代码版本选择。 方面包括基于对通过调用当前在计算机系统的处理器上执行的软件发出的方法的调用，确定指纹，其包括在主叫软件执行时在处理器中发生的行为序列的表示。 另一方面包括，基于确定指纹的匹配位于指纹表中的条目中，执行该方法的相关代码版本。 另一方面包括：基于确定不存在指纹匹配位于指纹表中的任何条目中：由计算机系统的编译器确定方法的新代码版本; 将指纹与新代码版本的标识符存储在指纹表中的新条目中; 并执行新的代码版本。

公开(公告)号：US09383996B2

公开(公告)日：2016-07-05

申请号：US13783337

申请日：2013-03-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jonathan D. Bradbury ,  Michael K. Gschwind ,  Christian Jacobi ,  Eric M. Schwarz ,  Timothy J. Slegel

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/455

CPC classification number: G06F9/30043 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30098 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/3824 ,  G06F9/3861 ,  G06F9/45516

Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.

公开(公告)号：US20160179634A1

公开(公告)日：2016-06-23

申请号：US14869850

申请日：2015-09-29

Applicant: International Business Machines Corporation

Inventor： Gregory W. Alexander ,  Khary J. Alexander ,  Ilya Granovsky ,  Christian Jacobi ,  Gregory Miaskovsky ,  James R. Mitchell

IPC: G06F11/16 ,  G06F11/30 ,  G06F11/07

CPC classification number: G06F11/073 ,  G06F1/3275 ,  G06F9/30 ,  G06F9/3826 ,  G06F9/3834 ,  G06F11/1666 ,  G06F11/3037 ,  Y02D10/13 ,  Y02D10/14

Abstract: A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises detecting memory address information corresponding to accessed data in a first instruction, and detecting memory address information corresponding to accessed data in a second instruction. The method further comprises comparing the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detecting, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. In addition the method comprise executing the second instruction using the accessed data from the first instruction and detecting an error from the execution of the second instruction.

Abstract translation: 本文描述了用于生成处理器的功能设计模型的计算机辅助设计系统中的方法。 该方法包括检测与第一指令中的访问数据相对应的存储器地址信息，以及检测与第二指令中的访问数据相对应的存储器地址信息。 该方法还包括比较与第一指令相对应的存储器地址信息和与第二指令相对应的存储器地址信息，并且基于比较来检测第一指令中的访问数据和第二指令中的访问数据是 在存储器件的相同数据范围内。 此外，该方法包括使用来自第一指令的访问数据执行第二指令，并从第二指令的执行中检测错误。

公开(公告)号：US20160162401A1

公开(公告)日：2016-06-09

申请号：US14811058

申请日：2015-07-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jonathan D. Bradbury ,  Michael K. Gschwind ,  Christian Jacobi ,  Timothy J. Slegel

IPC: G06F12/02 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F12/023 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/3824 ,  G06F12/0646 ,  G06F13/1652 ,  G06F2212/1044 ,  G06F2212/251 ,  G06F2212/656

Abstract: Embodiments relate to accessing data in a memory. A method for accessing data in a memory coupled to a processor is provided. The method receives a memory reference instruction for accessing data of a first size at an address in the memory. The method determines an alignment size of the address in the memory. The method accesses the data of the first size in one or more groups of data by accessing each group of data block concurrently. The groups of data have sizes that are multiples of the alignment size.

Abstract translation: 实施例涉及访问存储器中的数据。 提供了一种用于访问耦合到处理器的存储器中的数据的方法。 该方法接收用于在存储器中的地址处访问第一大小的数据的存储器参考指令。 该方法确定存储器中地址的对齐大小。 该方法通过同时访问每组数据块来访问一组或多组数据中的第一大小的数据。 数据组的大小是对齐大小的倍数。

公开(公告)号：US20160125055A1

公开(公告)日：2016-05-05

申请号：US14533265

申请日：2014-11-05

Applicant: International Business Machines Corporation

Inventor： Markus M. Helms ,  Christian Jacobi ,  Aditya N. Puranik ,  Parminder Singh

IPC: G06F17/30 ,  G06F17/27

Abstract: Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.

Abstract translation: 本发明的实施例提供了通过使用数据模式的统计发生来在一个转换周期中转换经常出现的数据模式来提高协处理器中的数据转换效率的系统和方法。 在一个实施例中，公开了一种包含转换器引擎的协处理器系统，转换器引擎包括解析器和转换器，输入缓冲器和结果存储器。 输入缓冲器被配置为将一组源数据传送到转换器引擎，转换器引擎将源数据从第一代码格式转换为第二代码格式，并将转换的源数据发送到结果存储。

公开(公告)号：US20160103774A1

公开(公告)日：2016-04-14

申请号：US14509533

申请日：2014-10-08

Applicant: International Business Machines Corporation

Inventor： Jonathan D. Bradbury ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Charles W. Gainey, JR. ,  Dan F. Greiner ,  Lisa C. Heller ,  Christian Jacobi ,  Jeffrey P. Kubala ,  Frank Lehnert ,  Bernd Nerz ,  Damian L. Osisek ,  Donald W. Schmidt ,  Timothy J. Slegel

IPC: G06F13/26

CPC classification number: G06F13/26 ,  G06F9/45558 ,  G06F9/46 ,  G06F2009/45579

Abstract: A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.

Abstract translation: 实现输入/输出（I / O）中断的修改的优先级路由的系统和方法。 系统和方法确定核心的I / O中断是否处于待决状态，并且根据确定I / O中断正在等待，核心的多个访客线程中的任何一个是否被启用用于中断的客线程处理 。 此外，系统和方法确定启用客户线程处理的多个访客线程中的至少一个是否处于等待状态，并且根据确定多个客机线程中的至少一个启用客机线程处理 处于等待状态，将I / O中断路由到客户线程处理并处于等待状态。

公开(公告)号：US20160103681A1

公开(公告)日：2016-04-14

申请号：US14511408

申请日：2014-10-10

Applicant: International Business Machines Corporation

Inventor： Khary J. Alexander ,  Jonathan T. Hsieh ,  Christian Jacobi ,  Martin Recktenwald

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F12/128 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/62

Abstract: A mechanism for simultaneous multithreading is provided. Responsive to performing a store instruction for a given thread of threads on a processor core and responsive to the core having ownership of a cache line in a cache, an entry of the store instruction is placed in a given store queue belonging to the given thread. The entry for the store instruction has a starting memory address and an ending memory address on the cache line. The starting memory addresses through ending memory addresses of load queues of the threads are compared on a byte-per-byte basis against the starting through ending memory address of the store instruction. Responsive to one memory address byte in the starting through ending memory addresses in the load queues overlapping with a memory address byte in the starting through ending memory address of the store instruction, the threads having the one memory address byte is flushed.

Abstract translation: 提供了同时多线程的机制。 响应于对处理器核心上的线程的给定线程执行存储指令并且响应于具有高速缓存中的高速缓存行的所有权的核心，存储指令的条目被放置在属于给定线程的给定存储队列中。 存储指令的条目具有起始存储器地址和高速缓存行上的结束存储器地址。 通过结束线程的加载队列的存储器地址的起始存储器地址以与存储指令的开始到结束存储器地址的字节/字节为基础进行比较。 通过结束存储指令的开始存储器地址的存储器地址中的存储器地址字节与负载队列中的存储器地址的结束来响应一个存储器地址字节，具有一个存储器地址字节的线程被刷新。

公开(公告)号：US09292443B2

公开(公告)日：2016-03-22

申请号：US13927322

申请日：2013-06-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Khary J. Alexander ,  Christian Jacobi ,  Martin Recktenwald ,  Timothy J. Slegel

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0815 ,  G06F12/0862

Abstract: Fetching a cache line into a plurality of caches of a multilevel cache system. The multilevel cache system includes at least a first cache, a second cache on a next higher level and a memory, the first cache being arranged to hold a subset of information of the second cache, the second cache being arranged to hold a subset of information of a next higher level cache or memory if no higher level cache exists. A fetch request is sent from one cache to the next cache in the multilevel cache system. The cache line is fetched in a particular state into one of the caches, and in another state into at least one of the other caches.

Abstract translation: 将高速缓存行提取到多级高速缓存系统的多个高速缓存中。 所述多级缓存系统至少包括第一高速缓存，下一较高级的第二高速缓存和存储器，所述第一高速缓存被配置为保存所述第二高速缓存的信息的子集，所述第二高速缓存被配置为保存信息的子集 的高级缓存或内存，如果没有更高级别的高速缓存存在。 从多个缓存系统向一个缓存发送一个提取请求到下一个缓存。 将高速缓存行以特定状态获取到其中一个高速缓存中，并且在另一状态中被进入至少一个高速缓存。

公开(公告)号：US09286076B2

公开(公告)日：2016-03-15

申请号：US14519553

申请日：2014-10-21

Applicant: International Business Machines Corporation

Inventor： Brenton F. Belmar ,  Mark S. Farrell ,  Christian Jacobi ,  Timothy J. Slegel

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/46

CPC classification number: G06F9/3857 ,  G06F9/30 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/466 ,  G06F9/467

Abstract: Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.

公开(公告)号：US09183146B2

公开(公告)日：2015-11-10

申请号：US14070692

申请日：2013-11-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christian Habermann ,  Christian Jacobi ,  Martin Recktenwald ,  Hans-Werner Tast

IPC: G06F13/00 ,  G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0811 ,  G06F2212/1024 ,  G06F2212/604

Abstract: A hierarchical cache structure includes at least one real indexed higher level cache with a directory and a unified cache array for data and instructions, and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache of a split real indexed second level cache includes a directory and a corresponding cache array connected to the real indexed third level cache. A data cache of the split second level cache includes a directory connected to the third level cache. An instruction cache of a split virtually indexed first level cache is connected to the second level instruction cache. A cache array of a data cache of the first level cache is connected to the cache array of the second level instruction cache and to the cache array of the third level cache. A directory of the first level data cache is connected to the second level instruction cache directory and to the third level cache directory.

Abstract translation: 分级缓存结构包括至少一个具有目录的真实索引高级缓存和用于数据和指令的统一高速缓存阵列，以及至少两个较低级别的高速缓存，每个高速缓存分离在指令高速缓存和数据高速缓存中。 分割的实际索引的二级高速缓存的指令高速缓存包括连接到实际索引的第三级高速缓存的目录和对应的高速缓存阵列。 分离的第二级高速缓存的数据高速缓存包括连接到第三级高速缓存的目录。 分割的虚拟索引的第一级高速缓存的指令高速缓存连接到第二级指令高速缓存。 第一级高速缓存的数据高速缓存的高速缓存阵列连接到第二级指令高速缓存的高速缓存阵列和第三级高速缓存的高速缓存阵列。 第一级数据高速缓存的目录连接到第二级指令高速缓存目录和第三级缓存目录。