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    MAGNETORESISTIVE RANDOM ACCESS MEMORY
    71.
    发明申请
    MAGNETORESISTIVE RANDOM ACCESS MEMORY 审中-公开
    磁力随机访问存储器

    公开(公告)号：US20140124880A1

    公开(公告)日：2014-05-08

    申请号：US13670148

    申请日：2012-11-06

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Daniel C. Worledge

    IPC: H01L43/02

    CPC classification number: H01L43/12 ,  G11C11/1675 ,  H01L27/222

    Abstract: A magnetic random access memory (MRAM) device includes at least one read line, at least one write line and a tunnel junction extending from the at least one read line toward the at least one write line. A heating line is connected to an opposite end of the tunnel junction from the at least one read line. The heating line is configured to supply heat to the tunnel junction to heat the tunnel junction based on current flowing through the heating line.

    Abstract translation: 磁性随机存取存储器（MRAM）装置包括至少一条读取线，至少一条写入线和从该至少一条读取线延伸至该至少一条写入线的隧道结。 加热线路与至少一条读取线路连接到隧道结的相对端。 加热管线被配置为基于流过加热管线的电流向隧道结加热以加热隧道结。

    Magnetic exchange coupled MTJ free layer having low switching current and high data retention
    72.
    发明授权
    Magnetic exchange coupled MTJ free layer having low switching current and high data retention 有权

    公开(公告)号：US12190925B2

    公开(公告)日：2025-01-07

    申请号：US16386490

    申请日：2019-04-17

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Guohan Hu ,  Daniel C. Worledge

    IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

    Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment.

    Spin transfer torque cell for magnetic random access memory
    76.
    发明授权
    Spin transfer torque cell for magnetic random access memory 有权

    公开(公告)号：US10326074B2

    公开(公告)日：2019-06-18

    申请号：US15671847

    申请日：2017-08-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Michael C. Gaidis ,  Janusz J. Nowak ,  Daniel C. Worledge

    IPC: H01L43/12 ,  H01L43/08 ,  H01F10/32 ,  H01F41/30 ,  B82Y40/00 ,  H01L43/02

    Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

    Secure off-chip MRAM
    77.
    发明授权
    Secure off-chip MRAM 有权

    公开(公告)号：US10170178B2

    公开(公告)日：2019-01-01

    申请号：US15590521

    申请日：2017-05-09

    Applicant: International Business Machines Corporation

    Inventor： John K. DeBrosse ,  William E. Hall ,  Hillery C. Hunter ,  Jeffrey A. Stuecheli ,  Daniel C. Worledge

    IPC: G11C11/30 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G06F11/22

    Abstract: Techniques for improving the security of nonvolatile memory such as magnetic random access memory (MRAM) are provided. In one aspect, a method of operating a nonvolatile memory chip is provided. The method includes: overwriting data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on. For example, all bits in the nonvolatile memory chip can be written to either i) a predetermined data state (e.g., a logic 1 or a logic 0) or ii) a random data state. A system is also provided that includes: a nonvolatile memory chip; and a writing circuit configured to overwrite data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on.

    In-situ annealing to improve the tunneling magneto-resistance of magnetic tunnel junctions
    79.
    发明授权
    In-situ annealing to improve the tunneling magneto-resistance of magnetic tunnel junctions 有权

    公开(公告)号：US09960348B2

    公开(公告)日：2018-05-01

    申请号：US15183421

    申请日：2016-06-15

    Applicant: International Business Machines Corporation

    Inventor： Guohan Hu ,  Daniel C. Worledge

    IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L27/105

    CPC classification number: H01L43/12 ,  H01L27/1052 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08

    Abstract: Embodiments are directed to a magnetic tunnel junction (MTJ) memory cell that includes a reference layer formed from a perpendicular magnetic anisotropy (PMA) reference layer and an interfacial reference layer. The MTJ further includes a free layer and a tunnel barrier positioned between the interfacial reference layer and the free layer. The tunnel barrier is configured to enable electrons to tunnel through the tunnel barrier between the interfacial reference layer and the free layer. A first in-situ alignment is provided between a tunnel barrier lattice structure of the tunnel barrier and an interfacial reference layer lattice structure of the interfacial reference layer. A second in-situ alignment is provided between the tunnel barrier lattice structure of the tunnel barrier and a free layer lattice structure of the free layer. The PMA reference layer lattice structure is not aligned with the interfacial reference layer lattice structure.

    In-situ annealing to improve the tunneling magneto-resistance of magnetic tunnel junctions
    80.
    发明授权
    In-situ annealing to improve the tunneling magneto-resistance of magnetic tunnel junctions 有权

    公开(公告)号：US09853208B2

    公开(公告)日：2017-12-26

    申请号：US14585435

    申请日：2014-12-30

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Guohan Hu ,  Daniel C. Worledge

    IPC: H01L43/12 ,  H01L43/02 ,  H01L43/10 ,  H01L43/08 ,  H01L27/105 ,  H01L27/22

    CPC classification number: H01L43/12 ,  H01L27/1052 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08

    Abstract: Embodiments are directed to a magnetic tunnel junction (MTJ) memory cell that includes a reference layer formed from a perpendicular magnetic anisotropy (PMA) reference layer and an interfacial reference layer. The MTJ further includes a free layer and a tunnel barrier positioned between the interfacial reference layer and the free layer. The tunnel barrier is configured to enable electrons to tunnel through the tunnel barrier between the interfacial reference layer and the free layer. A first in-situ alignment is provided between a tunnel barrier lattice structure of the tunnel barrier and an interfacial reference layer lattice structure of the interfacial reference layer. A second in-situ alignment is provided between the tunnel barrier lattice structure of the tunnel barrier and a free layer lattice structure of the free layer. The PMA reference layer lattice structure is not aligned with the interfacial reference layer lattice structure.

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