公开(公告)号：US20210151377A1

公开(公告)日：2021-05-20

申请号：US16685192

申请日：2019-11-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chi-Chun Liu ,  John C. Arnold ,  Dominik Metzler ,  Nelson Felix ,  Ashim Dutta

IPC: H01L23/538 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/762

Abstract: A method of forming a self-aligned top via is provided. The method includes forming a metallization layer on a substrate, and forming a hardmask layer on the metallization layer. The method further includes forming a pair of adjacent parallel mandrels on the hardmask layer with sidewall spacers on opposite sides of each mandrel. The method further includes forming a planarization layer on the exposed portions of the hardmask layer, mandrels, and sidewall spacers, and forming an opening in the planarization layer aligned between the adjacent parallel mandrels. The method further includes forming a spacer layer in the opening, and removing portions of the spacer layer to form a pair of spacer plugs between sections of the sidewall spacers.

公开(公告)号：US20210082697A1

公开(公告)日：2021-03-18

申请号：US16570603

申请日：2019-09-13

Applicant: International Business Machines Corporation

Inventor： Ekmini Anuja De Silva ,  Jing Guo ,  Luciana Meli ,  Nelson Felix

IPC: H01L21/033 ,  H01L21/027

Abstract: A method includes depositing a resist layer onto a hard mask layer to form a multi-layer patterning material film stack on a semiconductor substrate, directing patterning radiation onto the film stack to form a developed pattern in the resist layer and exposing the film stack to at least one gas precursor in connection with a sequential infiltration synthesis process. The film stack is configured to facilitate selective infiltration of the at least one gas precursor into the resist layer.

公开(公告)号：US20210049242A1

公开(公告)日：2021-02-18

申请号：US16539809

申请日：2019-08-13

Applicant: international Business Machines Corporation

Inventor： Scott Halle ,  Derren Dunn ,  Nelson Felix ,  Dhiraj Gupta

IPC: G06F17/50

Abstract: Techniques for semiconductor process flow disposition optimization using clamped Monte Carlo distribution are provided. In one aspect, a method for optimizing a semiconductor fabrication process includes: providing a model of the fabrication process; identifying sensitive parameters of the fabrication process using Monte Carlo simulations that sample sections of experimental parameter populations from the fabrication process as input to the model to determine parameters which impact an outcome of the Monte Carlo simulations, wherein the parameters which impact the outcome of the Monte Carlo simulations are the sensitive parameters; bounding the experimental parameter populations of the sensitive parameters to improve the outcome of the Monte Carlo simulations; and modifying the fabrication process based on the providing, identifying and bounding steps to improve an output of the fabrication process.

公开(公告)号：US20200292942A1

公开(公告)日：2020-09-17

申请号：US16299645

申请日：2019-03-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jing Guo ,  Bharat Kumar ,  Ekmini A. De Silva ,  Jennifer Church ,  Dario Goldfarb ,  Nelson Felix

IPC: G03F7/20 ,  H01L21/027 ,  G03F7/16 ,  G03F7/32

Abstract: A method of making an adhesion layer of an extreme ultraviolet (EUV) stack is presented. The method includes grafting an ultraviolet (UV) sensitive polymer brush on a hardmask, the polymer brush including a UV cleavable unit, depositing EUV resist over the polymer brush, exposing the EUV resist to remove the EUV resist in exposed areas by applying a developer, and flooding the exposed area with a UV light and a solvent developer to remove exposed portions of the polymer brush.

公开(公告)号：US20200272045A1

公开(公告)日：2020-08-27

申请号：US16282005

申请日：2019-02-21

Applicant: International Business Machines Corporation

Inventor： Nelson Felix ,  Luciana Meli Thompson ,  Ashim Dutta ,  Ekmini A. De Silva

IPC: G03F1/22 ,  H01L21/308 ,  G03F7/075

Abstract: Techniques for EUV resist pattern transfer using a graded hardmask are provided. In one aspect, a method of patterning is provided. The method includes: forming a graded hardmask on a device stack; depositing a resist onto the graded hardmask; patterning the resist to form a pattern in the resist having at least one feature; modifying at least one surface region to increase an etch rate of the graded hardmask; transferring the pattern from the resist to the graded hardmask; and transferring the pattern from the graded hardmask to at least one underlying layer of the device stack. A device structure formed by the patterning method is also provided.

公开(公告)号：US10755926B2

公开(公告)日：2020-08-25

申请号：US15817407

申请日：2017-11-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Abraham Arceo de la Pena ,  Ekmini Anuja De Silva ,  Nelson Felix

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/3215 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768

Abstract: The invention herein includes enhancing the surface of an amorphous silicon hardmask through implantation of nonpolar, hydrophobic elements, resulting in increased hydrophobicity and increased resist adhesion of the amorphous silicon surface. According to the invention, implanting the hydrophobic elements may involve introduction of the hydrophobic elements into the surface of the amorphous silicon by way of low energy implantation and plasma treatment. The implanted hydrophobic element may be Boron, Xenon, Fluorine, Phosphorus, a combination thereof, or other hydrophobic elements. According to the invention, the surface of the amorphous silicon is enhanced with 10-15% hydrophobic element, however in other embodiments, this composition may be adjusted as needed. In any case, however, the invention herein includes maintaining an etch selectivity of the bulk amorphous silicon hardmask.

公开(公告)号：US10658521B2

公开(公告)日：2020-05-19

申请号：US15980561

申请日：2018-05-15

Applicant: International Business Machines Corporation

Inventor： Indira Seshadri ,  Ekmini Anuja De Silva ,  Jing Guo ,  Ruqiang Bao ,  Muthumanickam Sankarapandian ,  Nelson Felix

IPC: H01L21/02 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.

公开(公告)号：US20200070150A1

公开(公告)日：2020-03-05

申请号：US16419684

申请日：2019-05-22

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Yann Mignot ,  Joshua T. Smith ,  Bassem M. Hamieh ,  Nelson Felix ,  Robert L. Bruce

IPC: B01L3/00 ,  B81C1/00 ,  B81B7/00

Abstract: A microfluidic chip with high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.

公开(公告)号：US20200050113A1

公开(公告)日：2020-02-13

申请号：US16657654

申请日：2019-10-18

Applicant: International Business Machines Corporation

Inventor： Ekmini Anuja De Silva ,  Indira Seshadri ,  Jing Guo ,  Ashim Dutta ,  Nelson Felix

IPC: G03F7/20 ,  H01L21/308 ,  H01L21/027 ,  G03F1/22 ,  H01L21/033 ,  G03F1/54

Abstract: A semiconductor structure comprises a semiconductor substrate, and a multi-layer patterning material film stack formed on the semiconductor substrate. The patterning material film stack comprises at least a hard mask layer and a resist layer formed over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on a developed pattern of the resist layer through inclusion in the hard mask layer of one or more materials inhibiting deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer. The hard mask layer illustratively comprises, for example, at least one of a grafted self-assembled monolayer configured to inhibit deposition of the metal-containing layer, and a grafted polymer brush material configured to inhibit deposition of the metal-containing layer.

公开(公告)号：US20190259601A1

公开(公告)日：2019-08-22

申请号：US16404404

申请日：2019-05-06

Applicant: International Business Machines Corporation

Inventor： Ekmini Anuja De Silva ,  Dario Goldfarb ,  Nelson Felix ,  Daniel Corliss ,  Rudy J. Wojtecki

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/033 ,  G03F7/09 ,  G03F7/20 ,  G03F7/26

Abstract: A semiconductor structure includes a semiconductor substrate and a multi-layer patterning material film stack formed on the semiconductor substrate. The patterning material film stack includes a resist layer formed over one or more additional layers. The semiconductor structure further includes a metal-containing top coat formed over the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.