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公开(公告)号：US10437951B2
公开(公告)日：2019-10-08
申请号：US15684006
申请日：2017-08-23
发明人： Ravi K. Bonam , Nelson Felix , Scott Halle , Luciana Meli
摘要： A method comprises: defining a set of rules for an inspection and detection of a defect in two or more electronic devices on a semiconductor chip, the set of rules being based on a modulation transfer function providing a response as contrast versus spatial frequency of the pattern spacings of the two or more electronic devices on the semiconductor chip; generating two or more care areas for two or more pattern spacings of the electronic devices on the semiconductor chip using a hierarchical set of spacing rules; and inspecting the two or more pattern spacings of the electronic devices on the semiconductor chip for defects.
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公开(公告)号：US20230280644A1
公开(公告)日：2023-09-07
申请号：US17653296
申请日：2022-03-03
IPC分类号： G03F1/24
CPC分类号： G03F1/24
摘要： Embodiments of present invention provide a method of forming an extreme ultraviolet (EUV) mask. The method includes subliming a radiation-sensitive material onto a surface of an EUV blank substrate; exposing the radiation-sensitive material to an ionizing radiation to form an EUV mask pattern; and removing a portion of the radiation-sensitive material from the surface of the EUV blank substrate where the portion of the radiation-sensitive material is unexposed to the ionizing radiation. An EUV mask made therefrom, and the related radiation-sensitive material are also provided.
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公开(公告)号：US20210082697A1
公开(公告)日：2021-03-18
申请号：US16570603
申请日：2019-09-13
发明人： Ekmini Anuja De Silva , Jing Guo , Luciana Meli , Nelson Felix
IPC分类号： H01L21/033 , H01L21/027
摘要： A method includes depositing a resist layer onto a hard mask layer to form a multi-layer patterning material film stack on a semiconductor substrate, directing patterning radiation onto the film stack to form a developed pattern in the resist layer and exposing the film stack to at least one gas precursor in connection with a sequential infiltration synthesis process. The film stack is configured to facilitate selective infiltration of the at least one gas precursor into the resist layer.
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公开(公告)号：US20220390845A1
公开(公告)日：2022-12-08
申请号：US17340300
申请日：2021-06-07
摘要： Alternating copolymers having hydrocarbon-substituted terminal units and repeat units each containing two different monomer units with extreme ultraviolet (EUV)-absorbing elements are disclosed. Alternating copolymers having organic terminal units and repeat units each containing a monomer unit with an EUV-absorbing element and an organic monomer unit are also disclosed. A process of forming a polymer resist, which includes providing an alternating copolymer having repeat units with at least one EUV-absorbing monomer unit and replacing end groups of the alternating copolymer with unreactive terminal units, is disclosed as well.
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公开(公告)号：US11194254B2
公开(公告)日：2021-12-07
申请号：US16676334
申请日：2019-11-06
摘要： Techniques for lithography process delay characterization and effective dose compensation are provided. In one aspect, a method of analyzing a lithography process includes: applying a photoresist to a wafer; performing a post-apply bake of the photoresist; patterning the photoresist with sequences of open frame base line exposures performed at doses of from about 92% E0 to about 98% E0, and ranges therebetween, at multiple fields of the wafer separated by intervening programmed delay intervals, wherein E0 is the photoresist dose-to-clear; performing a post-exposure bake of the photoresist; developing the photoresist; performing a full wafer inspection to generate a grayscale map of the wafer; and analyzing the grayscale map to determine whether the intervening programmed delay intervals had an effect on the open frame base line exposures during the lithography process. Exposure dose compensation can then be applied to maintain a constant effective dose.
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公开(公告)号：US20210132502A1
公开(公告)日：2021-05-06
申请号：US16676334
申请日：2019-11-06
摘要： Techniques for lithography process delay characterization and effective dose compensation are provided. In one aspect, a method of analyzing a lithography process includes: applying a photoresist to a wafer; performing a post-apply bake of the photoresist; patterning the photoresist with sequences of open frame base line exposures performed at doses of from about 92% E0 to about 98% E0, and ranges therebetween, at multiple fields of the wafer separated by intervening programmed delay intervals, wherein E0 is the photoresist dose-to-clear; performing a post-exposure bake of the photoresist; developing the photoresist; performing a full wafer inspection to generate a grayscale map of the wafer; and analyzing the grayscale map to determine whether the intervening programmed delay intervals had an effect on the open frame base line exposures during the lithography process. Exposure dose compensation can then be applied to maintain a constant effective dose.
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公开(公告)号：US11906901B2
公开(公告)日：2024-02-20
申请号：US17340300
申请日：2021-06-07
CPC分类号： G03F7/0392 , G03F7/0042 , G03F7/0043 , G03F7/2004
摘要： Alternating copolymers having hydrocarbon-substituted terminal units and repeat units each containing two different monomer units with extreme ultraviolet (EUV)-absorbing elements are disclosed. Alternating copolymers having organic terminal units and repeat units each containing a monomer unit with an EUV-absorbing element and an organic monomer unit are also disclosed. A process of forming a polymer resist, which includes providing an alternating copolymer having repeat units with at least one EUV-absorbing monomer unit and replacing end groups of the alternating copolymer with unreactive terminal units, is disclosed as well.
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公开(公告)号：US10707326B2
公开(公告)日：2020-07-07
申请号：US16282384
申请日：2019-02-22
发明人： Chi-Chun Liu , Sanjay Mehta , Luciana Meli , Muthumanickam Sankarapandian , Kristin Schmidt , Ankit Vora
IPC分类号： H01L29/66 , H01L21/8238 , H01L29/78 , H01L29/08 , H01L27/088 , H01L29/423 , H01L29/786 , H01L29/417
摘要： A vertical field-effect transistor and a method for fabricating the same. The vertical field-effect transistor includes a substrate and a bottom source/drain region. The vertical field-effect transistor also includes at least one fin structure, and further includes a bottom spacer layer. The bottom spacer layer has a substantially uniform thickness with a thickness variation of less than 3 nm. A gate structure contacts the bottom spacer layer and at least one fin structure. The method includes forming a structure including a substrate, a source/drain region, and one or more fins. A polymer brush spacer is formed in contact with at least sidewalls of the one or more fins. A polymer brush layer is formed in contact with at least the source/drain region and the polymer brush spacer. The polymer brush spacer is removed. Then, the polymer brush layer is reflowed to the sidewalls of the at least one fin.
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公开(公告)号：US20190065634A1
公开(公告)日：2019-02-28
申请号：US15684006
申请日：2017-08-23
发明人： Ravi K. Bonam , Nelson Felix , Scott Halle , Luciana Meli
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5081 , G06F2217/08 , G06F2217/14 , H01J37/32009
摘要： A method comprises: defining a set of rules for an inspection and detection of a defect in two or more electronic devices on a semiconductor chip, the set of rules being based on a modulation transfer function providing a response as contrast versus spatial frequency of the pattern spacings of the two or more electronic devices on the semiconductor chip; generating two or more care areas for two or more pattern spacings of the electronic devices on the semiconductor chip using a hierarchical set of spacing rules; and inspecting the two or more pattern spacings of the electronic devices on the semiconductor chip for defects.
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公开(公告)号：US11561481B2
公开(公告)日：2023-01-24
申请号：US16932983
申请日：2020-07-20
摘要： Techniques for using open frame (E0) exposures for lithographic tool track/cluster monitoring are provided. In one aspect, a method for monitoring a lithographic process includes: performing open frame exposures E0 of at least one wafer coated with a photoresist using a photolithography tool; baking and developing the at least one wafer; performing a defect inspection of the at least one wafer to generate a haze map; grouping haze data from the haze map; and analyzing the haze data to identify a maximum E0 response dose E′.
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