中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

140 records (took 0.029 seconds)

    ENHANCED NVDIMM ARCHITECTURE
    73.
    发明申请
    ENHANCED NVDIMM ARCHITECTURE 审中-公开

    公开(公告)号：US20200020360A1

    公开(公告)日：2020-01-16

    申请号：US16033385

    申请日：2018-07-12

    Applicant: International Business Machines Corporation

    Inventor： Trinadhachari Kosuru ,  Janani Swaminathan ,  Saravanan Sethuraman ,  Adam J. McPadden

    IPC: G11C5/04 ,  G11C14/00 ,  G06F12/02 ,  G06F3/06

    Abstract: Aspects of the present disclosure relate to a memory module having a volatile memory, a high speed non-volatile memory, and a non-volatile memory. The memory module can allow write mirroring to the volatile memory and high speed non-volatile memory simultaneously. An I/O request is received. A determination is made whether the I/O request is a write or a read. In response to determining that the I/O request is a read, data included in the high speed non-volatile memory is transferred to the non-volatile memory. In response to determining that the I/O request is a write, at least one location to write data of the write is determined based on decoding bits of the write command. The data of the write can then be written to the at least one location.

    WRITE MANAGEMENT FOR INCREASING NON-VOLATILE MEMORY RELIABILITY
    74.
    发明申请
    WRITE MANAGEMENT FOR INCREASING NON-VOLATILE MEMORY RELIABILITY 审中-公开

    公开(公告)号：US20190339909A1

    公开(公告)日：2019-11-07

    申请号：US16417486

    申请日：2019-05-20

    Applicant: International Business Machines Corporation

    Inventor： Saravanan Sethuraman ,  Venkata K. Tavva ,  Adam J. McPadden ,  Hillery Hunter

    IPC: G06F3/06 ,  G06F12/02

    Abstract: A computer-implemented method, according to one embodiment, includes: determining a current temperature associated with an intended storage location in memory for data in a write request, determining a percentage of first logical states included in a binary representation of the data in the received write request, selecting a write management operation in response to determining that the current temperature associated with the intended storage location is outside a predetermined range, and sending one or more instructions to perform the write management operation. Moreover, the write management operation corresponds to the determined percentage of first logical states included in the binary representation. Other systems, methods, and computer program products are described in additional embodiments.

    Delay programming requests in flash memory
    76.
    发明授权
    Delay programming requests in flash memory 有权

    公开(公告)号：US10347346B2

    公开(公告)日：2019-07-09

    申请号：US15834496

    申请日：2017-12-07

    Applicant: International Business Machines Corporation

    Inventor： Saravanan Sethuraman ,  Gary A. Tressler ,  Harish Venkataraman

    IPC: G06F12/00 ,  G06F3/06 ,  G11C16/32 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

    Abstract: Embodiments herein describe a memory system that queues program requests to a block of flash memory until a predefined threshold is reached. That is, instead of performing program requests to write data into the block as the requests are received, the memory system queues the requests until the threshold is satisfied. Once the buffer for the block includes the threshold amount of program requests, the memory system performs the stored requests. In one embodiment, the memory system erases all the pages in the block before writing the new data in the program requests into the destination pages. The data that was originally stored in the pages that are not destination pages is rewritten into the pages. In this example, the queued program requests can be written into the pages using one erase and write step rather than individual erase and write steps for each of the requests.

    POWER MANAGEMENT IN MULTI-CHANNEL 3D STACKED DRAM
    78.
    发明申请
    POWER MANAGEMENT IN MULTI-CHANNEL 3D STACKED DRAM 审中-公开

    公开(公告)号：US20190033952A1

    公开(公告)日：2019-01-31

    申请号：US15684332

    申请日：2017-08-23

    Applicant: International Business Machines Corporation

    Inventor： Kevin M. Mcilvain ,  Saravanan Sethuraman ,  Warren E. Maule ,  Kyu-hyoun Kim

    IPC: G06F1/32 ,  G06F9/44

    Abstract: A three-dimensional stacked (3DS) memory module includes multiple memory chips and a data I/O chip physically integrated into the 3D stack. The data I/O chip includes multiple data interfaces and multiple respectively corresponding data buffers. A memory controller routes data traffic through all available data interfaces for maximum bandwidth. In some circumstances, the memory controller directs the data I/O chip to shut down (de-activate) one or more of the data interfaces (for example, to reduce power consumption of the memory module). All subsequent data traffic to and from the memory module is routed through the remaining active interfaces. All physical addresses in the 3DS memory module are addressable through the remaining active interfaces. In some circumstances, the memory controller directs the data I/O chip to re-activate some or all of the de-activated data interfaces. Once re-activated, subsequent data traffic to and from the memory module can again be routed through all active interfaces.

Patent Agency Ranking