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    Workfunction metal stacks for a final metal gate
    72.
    发明授权
    Workfunction metal stacks for a final metal gate 有权
    用于最终金属门的功能金属堆叠

    公开(公告)号：US08790973B2

    公开(公告)日：2014-07-29

    申请号：US13445475

    申请日：2012-04-12

    申请人： Thilo Scheiper ,  Jan Hoentschel

    发明人： Thilo Scheiper ,  Jan Hoentschel

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842

    摘要： Transistor devices are formed with a pMOS and an nMOS workfunction stack of substantially equal thickness after gate patterning. Embodiments include forming n-type and p-type areas in a substrate, forming a pMOS workfunction metal stack layer on both areas, forming a hardmask layer on the pMOS workfunction metal stack layer on the n-type area, removing the pMOS workfunction metal stack layer from the p-type area, forming an nMOS workfunction metal stack layer on the p-type area and on the hardmask layer, and removing the nMOS workfunction metal stack layer from the hardmask layer.

    摘要翻译： 在栅极图案化之后，晶体管器件由具有基本相等厚度的pMOS和nMOS功函数堆叠形成。 实施例包括在基板中形成n型和p型区域，在两个区域上形成pMOS功函数金属堆叠层，在n型区域上的pMOS功函数金属堆叠层上形成硬掩模层，去除pMOS功函数金属堆 层，在p型区域和硬掩模层上形成nMOS功函数金属堆叠层，并从硬掩模层去除nMOS功函数金属堆叠层。

    Predoped semiconductor material for a high-K metal gate electrode structure of P- and N-channel transistors
    74.
    发明授权
    Predoped semiconductor material for a high-K metal gate electrode structure of P- and N-channel transistors 有权
    用于P-型和N沟道晶体管的高K金属栅电极结构的预制半导体材料

    公开(公告)号：US08536036B2

    公开(公告)日：2013-09-17

    申请号：US12905711

    申请日：2010-10-15

    申请人： Sven Beyer ,  Jan Hoentschel ,  Uwe Griebenow ,  Thilo Scheiper

    发明人： Sven Beyer ,  Jan Hoentschel ,  Uwe Griebenow ,  Thilo Scheiper

    IPC分类号： H01L21/425 ,  H01L21/28 ,  H01L21/44

    CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/7848

    摘要： In a process strategy for forming high-k metal gate electrode structures in an early manufacturing phase, a predoped semiconductor material may be used in order to reduce the Schottky barrier between the semiconductor material and the conductive cap material of the gate electrode structures. Due to the substantially uniform material characteristics of the predoped semiconductor material, any patterning-related non-uniformities during the complex patterning process of the gate electrode structures may be reduced. The predoped semiconductor material may be used for gate electrode structures of complementary transistors.

    摘要翻译： 在用于在早期制造阶段形成高k金属栅电极结构的工艺策略中，可以使用预制半导体材料，以便减少半导体材料与栅电极结构的导电盖材料之间的肖特基势垒。 由于预制半导体材料的材料特性基本上均匀，可能会降低栅电极结构复杂构图工艺过程中任何与图案相关的不均匀性。 预制半导体材料可用于互补晶体管的栅电极结构。

    FIELD EFFECT TRANSISTORS FOR A FLASH MEMORY COMPRISING A SELF-ALIGNED CHARGE STORAGE REGION
    77.
    发明申请
    FIELD EFFECT TRANSISTORS FOR A FLASH MEMORY COMPRISING A SELF-ALIGNED CHARGE STORAGE REGION 有权
    用于包含自对准电荷存储区域的闪存存储器的场效应晶体管

    公开(公告)号：US20110211394A1

    公开(公告)日：2011-09-01

    申请号：US12939282

    申请日：2010-11-04

    申请人： Thilo Scheiper ,  Sven Beyer ,  Uwe Griebenow ,  Jan Hoentschel

    发明人： Thilo Scheiper ,  Sven Beyer ,  Uwe Griebenow ,  Jan Hoentschel

    IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L21/336

    CPC分类号： H01L29/788 ,  G11C16/0425 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

    摘要： Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.

    摘要翻译： 可以在自对准电荷存储区域的基础上提供用于半导体器件中的闪存区域的存储晶体管。 为此，可以在一些说明性实施例中提供浮动间隔元件，而在其他情况下，在替换栅极方法期间，电荷存储区域可以以自对准方式有效地嵌入电极材料中。 因此，可以不再需要用于图案化电荷存储区域的附加复杂光刻工艺，可以实现增强的位密度。

    STRAIN MEMORIZATION IN STRAINED SOI SUBSTRATES OF SEMICONDUCTOR DEVICES
    78.
    发明申请
    STRAIN MEMORIZATION IN STRAINED SOI SUBSTRATES OF SEMICONDUCTOR DEVICES 有权
    半导体器件的应变SOI衬底中的应变存储

    公开(公告)号：US20110210427A1

    公开(公告)日：2011-09-01

    申请号：US12917870

    申请日：2010-11-02

    申请人： Jan Hoentschel ,  Sven Beyer ,  Uwe Griebenow ,  Thilo Scheiper

    发明人： Jan Hoentschel ,  Sven Beyer ,  Uwe Griebenow ,  Thilo Scheiper

    IPC分类号： H01L29/06 ,  H01L21/3115

    CPC分类号： H01L21/3081 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7849

    摘要： In sophisticated semiconductor devices, the initial strain component of a globally strained semiconductor layer may be substantially preserved during the formation of shallow trench isolations by using a rigid mask material, which may efficiently avoid or reduce a deformation of the semiconductor islands upon patterning the isolation trenches. Consequently, selected regions with high internal stress levels may be provided, irrespective of the height-to-length aspect ratio, which may limit the application of globally strained semiconductor layers in conventional approaches. Furthermore, in some illustrative embodiments, active regions of substantially relaxed strain state or of inverse strain type may be provided in addition to the highly strained active regions, thereby enabling an efficient process strategy for forming complementary transistors.

    摘要翻译： 在复杂的半导体器件中，通过使用刚性掩模材料可以在形成浅沟槽隔离期间实质上保留全局应变半导体层的初始应变分量，这可以有效地避免或减少图案化隔离沟槽时半导体岛的变形 。 因此，可以提供具有高内应力水平的选定区域，而不考虑高度 - 长度的纵横比，这可能限制在常规方法中全局应变半导体层的应用。 此外，在一些说明性实施例中，除了高应变活性区域之外，还可以提供基本上松弛的应变状态或逆应变类型的有源区，从而实现用于形成互补晶体管的有效的工艺策略。

    Methods of Forming Semiconductor Devices with Embedded Semiconductor Material as Source/Drain Regions Using a Reduced Number of Spacers
    80.
    发明申请
    Methods of Forming Semiconductor Devices with Embedded Semiconductor Material as Source/Drain Regions Using a Reduced Number of Spacers 有权
    用嵌入式半导体材料形成半导体器件作为源/漏区域的方法使用减少的间隔数

    公开(公告)号：US20130302956A1

    公开(公告)日：2013-11-14

    申请号：US13470454

    申请日：2012-05-14

    申请人： Stefan Flachowsky ,  Ricardo P. Mikalo ,  Jan Hoentschel

    发明人： Stefan Flachowsky ,  Ricardo P. Mikalo ,  Jan Hoentschel

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

    摘要： In one example, a method disclosed herein includes the steps of forming a gate structure for a first transistor and a second transistor above a semiconducting substrate, forming a liner layer above the gate structures and performing a plurality of extension ion implant processes through the liner layer to form extension implant regions in the substrate for the first transistor and the second transistor. The method further includes forming a first sidewall spacer proximate the gate structure for the first transistor and a patterned hard mask layer positioned above the second transistor, performing at least one etching process to remove the first sidewall spacer, the patterned hard mask layer and the liner layer, forming a second sidewall spacer proximate both of the gate structures and performing a plurality of source/drain ion implant processes to form deep source/drain implant regions in the substrate for the first transistor and the second transistor.

    摘要翻译： 在一个示例中，本文公开的方法包括以下步骤：在半导体衬底上形成用于第一晶体管和第二晶体管的栅极结构，在栅极结构上方形成衬底层，并通过衬底层执行多个延伸离子注入工艺 以在第一晶体管和第二晶体管的衬底中形成延伸注入区。 该方法还包括形成靠近第一晶体管的栅极结构的第一侧壁隔离物和位于第二晶体管上方的图案化硬掩模层，执行至少一个蚀刻工艺以去除第一侧壁间隔物，图案化硬掩模层和衬垫 形成靠近两个栅极结构的第二侧壁间隔件，并且执行多个源极/漏极离子注入工艺以在用于第一晶体管和第二晶体管的衬底中形成深源极/漏极注入区域。