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    WORKFUNCTION METAL STACKS FOR A FINAL METAL GATE
    3.
    发明申请
    WORKFUNCTION METAL STACKS FOR A FINAL METAL GATE 有权
    用于最终金属门的功能金属堆叠

    公开(公告)号：US20130270645A1

    公开(公告)日：2013-10-17

    申请号：US13445475

    申请日：2012-04-12

    申请人： Thilo Scheiper ,  Jan Hoentschel

    发明人： Thilo Scheiper ,  Jan Hoentschel

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823842

    摘要： Transistor devices are formed with a pMOS and an nMOS workfunction stack of substantially equal thickness after gate patterning. Embodiments include forming n-type and p-type areas in a substrate, forming a pMOS workfunction metal stack layer on both areas, forming a hardmask layer on the pMOS workfunction metal stack layer on the n-type area, removing the pMOS workfunction metal stack layer from the p-type area, forming an nMOS workfunction metal stack layer on the p-type area and on the hardmask layer, and removing the nMOS workfunction metal stack layer from the hardmask layer.

    摘要翻译： 在栅极图案化之后，晶体管器件由具有基本相等厚度的pMOS和nMOS功函数堆叠形成。 实施例包括在基板中形成n型和p型区域，在两个区域上形成pMOS功函数金属堆叠层，在n型区域上的pMOS功函数金属堆叠层上形成硬掩模层，去除pMOS功函数金属堆 层，在p型区域和硬掩模层上形成nMOS功函数金属堆叠层，并从硬掩模层去除nMOS功函数金属堆叠层。

    Methods of forming stressed silicon-carbon areas in an NMOS transistor
    4.
    发明授权
    Methods of forming stressed silicon-carbon areas in an NMOS transistor 有权
    在NMOS晶体管中形成应力硅 - 碳区域的方法

    公开(公告)号：US08536034B2

    公开(公告)日：2013-09-17

    申请号：US13216921

    申请日：2011-08-24

    申请人： Stefan Flachowsky ,  Ralf Illgen ,  Thilo Scheiper ,  Jan Hoentschel

    发明人： Stefan Flachowsky ,  Ralf Illgen ,  Thilo Scheiper ,  Jan Hoentschel

    IPC分类号： H01L21/425

    CPC分类号： H01L21/26513 ,  H01L21/26526 ,  H01L29/7848

    摘要： Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate.

    摘要翻译： 这里公开了在NMOS晶体管器件中形成应力硅 - 碳区域的各种方法。 在一个实例中，本文公开的方法包括在包括多个N掺杂区域的半导体衬底的表面上方形成无定形碳层，并对无定形碳层进行离子注入工艺以将碳原子从层 并且将移动的碳原子驱动到衬底中的N掺杂区域中。

    Methods of Making Transistor Devices with Elevated Source/Drain Regions to Accommodate Consumption During Metal Silicide Formation Process
    5.
    发明申请
    Methods of Making Transistor Devices with Elevated Source/Drain Regions to Accommodate Consumption During Metal Silicide Formation Process 有权
    在金属硅化物形成过程中制造具有升高的源极/排水区域的晶体管器件以容纳消耗的方法

    公开(公告)号：US20130178034A1

    公开(公告)日：2013-07-11

    申请号：US13345922

    申请日：2012-01-09

    申请人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

    发明人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66628 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

    摘要： Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region.

    摘要翻译： 本文公开了具有双金属硅化物区域的各种半导体器件以及制造这种器件的各种方法。 本文公开的一种说明性方法包括以下步骤：形成位于半导体衬底的表面上方的源极/漏极区的上部，其中源极/漏极区的上部具有位于表面上方的上表面 以至少等于待形成在源/漏区上部的金属硅化物区域的目标厚度的距离，并在源/漏区的上部形成金属硅化物区域。

    Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement
    6.
    发明授权
    Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement 有权
    通过增加掺杂剂约束，包括高k金属栅极堆叠的PFET晶体管的性能增强

    公开(公告)号：US08404550B2

    公开(公告)日：2013-03-26

    申请号：US12905383

    申请日：2010-10-15

    申请人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

    发明人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66651

    摘要： In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.

    摘要翻译： 在包含高k金属栅电极结构的P沟道晶体管中，至少在阈值调节半导体材料（例如硅/锗材料）中可以通过掺入扩散阻挡物质获得优异的掺杂剂分布，例如 在形成阈值调节半导体材料之前。 因此，漏极和源极延伸区域可以被提供有高的掺杂剂浓度，以获得目标米勒电容，而不会导致低于阈值调节半导体材料的不适当的掺杂剂扩散，否则可能导致增加的漏电流和增加的穿孔风险 事件

    Semiconductor device substrate with embedded stress region, and related fabrication methods
    7.
    发明授权
    Semiconductor device substrate with embedded stress region, and related fabrication methods 有权
    具有嵌入应力区域的半导体器件基板及相关制造方法

    公开(公告)号：US08329551B2

    公开(公告)日：2012-12-11

    申请号：US12947460

    申请日：2010-11-16

    申请人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

    发明人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

    IPC分类号： H01L21/20

    CPC分类号： H01L29/1054 ,  H01L29/66651

    摘要： A semiconductor device substrate is presented here. The semiconductor device substrate includes a layer of first semiconductor material having a first lattice constant, a region of second semiconductor material located in the layer of first semiconductor material, and a layer of epitaxially grown third semiconductor material overlying the layer of first semiconductor material and overlying the region of second semiconductor material. The second semiconductor material has a second lattice constant that is different than the first lattice constant. Moreover, the layer of epitaxially grown third semiconductor material exhibits a stressed zone overlying the region of second semiconductor material. The stressed zone has a third lattice constant that is different than the first lattice constant.

    摘要翻译： 这里介绍一种半导体器件基板。 半导体器件衬底包括具有第一晶格常数的第一半导体材料层，位于第一半导体材料层中的第二半导体材料的区域和覆盖在第一半导体材料层上的外延生长的第三半导体材料层 第二半导体材料的区域。 第二半导体材料具有与第一晶格常数不同的第二晶格常数。 此外，外延生长的第三半导体材料层表现出覆盖第二半导体材料区域的应力区域。 应力区具有不同于第一晶格常数的第三晶格常数。

    Complementary stress liner to improve DGO/AVT devices and poly and diffusion resistors
    8.
    发明授权
    Complementary stress liner to improve DGO/AVT devices and poly and diffusion resistors 有权
    互补应力衬垫，用于改善DGO / AVT器件和聚和扩散电阻器

    公开(公告)号：US08324041B2

    公开(公告)日：2012-12-04

    申请号：US13023794

    申请日：2011-02-09

    申请人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

    发明人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

    IPC分类号： H01L21/8238

    CPC分类号： H01L28/20 ,  H01L29/78 ,  H01L29/7843

    摘要： Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.

    摘要翻译： 通过使用互补应力衬垫，在长沟道半导体器件和电阻器中电子迁移率和空穴迁移率得到改善。 实施例包括在衬底上形成长沟道半导体器件，并在半导体器件上形成互补应力衬垫。 实施例包括在衬底上形成电阻器，并通过在电阻器上形成互补应力衬垫来调节电阻器的电阻。 使用压缩应力衬垫来改善n型器件中的电子迁移率，并且使用拉伸应力衬垫来改善p型器件中的空穴迁移率。

    Dual Cavity Etch for Embedded Stressor Regions
    9.
    发明申请
    Dual Cavity Etch for Embedded Stressor Regions 审中-公开
    嵌入式应力区域的双腔蚀刻

    公开(公告)号：US20120292637A1

    公开(公告)日：2012-11-22

    申请号：US13109134

    申请日：2011-05-17

    申请人： Sven Beyer ,  Peter Baars ,  Jan Hoentschel ,  Thilo Scheiper

    发明人： Sven Beyer ,  Peter Baars ,  Jan Hoentschel ,  Thilo Scheiper

    IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/20

    CPC分类号： H01L21/823807 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    摘要： Generally, the present disclosure is directed to methods for forming embedded stressor regions in semiconductor devices such as transistor elements and the like. One illustrative method disclosed herein includes forming a first material in first cavities formed in a first active area adjacent to a first channel region of a semiconductor device, wherein the first material induces a first stress in the first channel region. The method also includes, among other things, forming a second material in second cavities formed in a second active area adjacent to a second channel region of the semiconductor device, wherein the second material induces a second stress in the second channel region that is of an opposite type of the first stress in the first channel region, and wherein the first and second cavities are formed during a common etch process.

    摘要翻译： 通常，本公开涉及在诸如晶体管元件等的半导体器件中形成嵌入的应力源区域的方法。 本文公开的一种说明性方法包括在与半导体器件的第一沟道区相邻的第一有源区中形成的第一空腔中形成第一材料，其中第一材料在第一沟道区域中引起第一应力。 该方法还包括在形成在与半导体器件的第二沟道区相邻的第二有源区中的第二腔中形成第二材料，其中第二材料在第二沟道区域中引起第二应力 在第一通道区域中相反类型的第一应力，并且其中第一和第二空腔在公共蚀刻工艺期间形成。