公开(公告)号：US07378713B2

公开(公告)日：2008-05-27

申请号：US11552704

申请日：2006-10-25

申请人： Peng-Fu Hsu ,  Fong-Yu Yen ,  Yi-Shien Mor ,  Huan-Just Lin ,  Ying Jin ,  Hun-Jan Tao

发明人： Peng-Fu Hsu ,  Fong-Yu Yen ,  Yi-Shien Mor ,  Huan-Just Lin ,  Ying Jin ,  Hun-Jan Tao

IPC分类号： H01L27/092 ,  H01L29/423

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

摘要： Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.

摘要翻译： 具有双金属栅极结构的半导体器件及其制造方法。 提供了具有由绝缘层分隔开的第一掺杂区域和第二掺杂区域的半导体衬底。 在第一掺杂区上形成第一金属栅叠层，在第二掺杂区上形成第二金属栅叠层。 密封层设置在第一栅极堆叠和第二栅极叠层的侧壁上。 第一金属栅叠层包括界面层，界面层上的高k电介质层，高k电介质层上的第一金属层，第一金属层上的金属插入层，金属上的第二金属层 插入层和第二金属层上的多晶硅层。 第二金属栅堆叠包括界面层，界面层上的高k电介质层，高k电介质层上的第二金属层和第二金属层上的多晶硅层。

公开(公告)号：US20080093675A1

公开(公告)日：2008-04-24

申请号：US11583634

申请日：2006-10-18

申请人： Liang-Gi Yao ,  Shiang-Bau Wang ,  Huan-Just Lin ,  Peng-Fu Hsu ,  Jin Ying ,  Hun-Jan Tao

发明人： Liang-Gi Yao ,  Shiang-Bau Wang ,  Huan-Just Lin ,  Peng-Fu Hsu ,  Jin Ying ,  Hun-Jan Tao

IPC分类号： H01L29/76

CPC分类号： H01L21/823835 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor structure includes a substrate, a gate stack on the substrate, a source/drain region adjacent the gate stack, a source/drain silicide region on the source/drain region, a protection layer on the source/drain silicide region, wherein a region over the gate stack is substantially free from the protection layer, and a contact etch stop layer (CESL) having a stress over the protection layer and extending over the gate stack.

摘要翻译： 半导体结构包括衬底，衬底上的栅极堆叠，与栅极堆叠相邻的源极/漏极区域，源极/漏极区域上的源极/漏极硅化物区域，源极/漏极硅化物区域上的保护层，其中 栅极叠层上的区域基本上没有保护层，以及在保护层上方并且在栅极堆叠上延伸的接触蚀刻停止层（CESL）。

公开(公告)号：US07301645B2

公开(公告)日：2007-11-27

申请号：US11053300

申请日：2005-02-07

申请人： Shiang-Bau Wang ,  Yuan-Hung Chiu ,  Hun-Jan Tao ,  Chao-Tzung Tsai

发明人： Shiang-Bau Wang ,  Yuan-Hung Chiu ,  Hun-Jan Tao ,  Chao-Tzung Tsai

IPC分类号： G01B11/02

CPC分类号： H01L22/20

摘要： A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upon the optical interference endpoint signal the critical dimension of the structural element.

摘要翻译： 提供一种监测集成电路中的结构元件的关键尺寸的方法，包括以下步骤：收集在蚀刻一个或多个层期间产生的光学干涉终点信号以形成结构元件; 以及基于所述光学干涉终点信号确定所述结构元件的临界尺寸。

公开(公告)号：US07294544B1

公开(公告)日：2007-11-13

申请号：US09249254

申请日：1999-02-12

申请人： Yen-Shih Ho ,  Jau-Yuann Chung ,  Chun-Hon Chen ,  Hun-Jan Tao

发明人： Yen-Shih Ho ,  Jau-Yuann Chung ,  Chun-Hon Chen ,  Hun-Jan Tao

IPC分类号： H01L21/336

CPC分类号： H01L21/8221 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating an improved metal-insulator-metal capacitor is achieved. An insulating layer is provided overlying conducting lines on a semiconductor substrate. Via openings through the insulating layer to the conducting lines are filled with metal plugs. A first metal layer is deposited overlying the insulating layer and the metal plugs. A capacitor dielectric layer is deposited overlying the first metal layer wherein capacitor dielectric layer is deposited as a dual layer, each layer deposited within a separate chamber whereby pinholes are eliminated. A second metal layer and a barrier metal layer are deposited overlying the capacitor dielectric layer. The second metal layer and the barrier metal layer are patterned to form a top plate electrode. Thereafter, the capacitor dielectric layer and the first metal layer are patterned to form a bottom plate electrode completing fabrication of a metal-insulator-metal capacitor.

摘要翻译： 实现了一种制造改进的金属 - 绝缘体 - 金属电容器的方法。 在半导体衬底上覆盖导电线的绝缘层。 通过绝缘层到导线的开口填充有金属插头。 沉积在绝缘层和金属插头上的第一金属层。 电容器电介质层沉积在第一金属层上，其中电容器电介质层被沉积为双层，每层沉积在单独的室内，由此消除针孔。 沉积在电容器介电层上的第二金属层和阻挡金属层。 将第二金属层和阻挡金属层图案化以形成顶板电极。 此后，对电容器电介质层和第一金属层进行图案化以形成完成金属 - 绝缘体 - 金属电容器的制造的底板电极。

公开(公告)号：USRE39913E1

公开(公告)日：2007-11-06

申请号：US10443924

申请日：2003-05-22

申请人： Hun-Jan Tao ,  Huan-Just Lin ,  Fang-Cheng Chen

发明人： Hun-Jan Tao ,  Huan-Just Lin ,  Fang-Cheng Chen

IPC分类号： G03F9/00

CPC分类号： G03F7/70625 ,  G03F7/40 ,  H01L22/20 ,  Y10S438/949

摘要： The invention is a process for reducing variations in CD from wafer to wafer. It begins by increasing all line widths in the original pattern data file by a fixed amount that is sufficient to ensure that all lines will be wider than the lowest acceptable CD value. Using a reticle generated from this modified data file, the pattern is formed in photoresist and the resulting CD value is determined. If this turns out be outside (above) the acceptable CD range, the amount of deviation from the ideal CD value is determined and fed into suitable software that calculates the control parameters (usually time) for an ashing routine. After ashing, the lines will have been reduced in width by the amount necessary to obtain the correct CD. A fringe benefit of this trimming process is that edge roughness of the photoresist lines is reduced and line feet are removed.

摘要翻译： 本发明是减少CD从晶片到晶片的变化的方法。 它首先将原始图案数据文件中的所有行宽增加一个固定的量，这足以确保所有行都比最低可接受的CD值宽。 使用由该修改的数据文件生成的掩模版，在光致抗蚀剂中形成图案，并确定所得到的CD值。 如果事实证明在可接受的CD范围之外（以上），则确定与理想CD值的偏差量，并将其馈送到计算灰化程序的控制参数（通常为时间）的合适软件中。 灰化后，线条的宽度减小了获得正确CD所需的量。 这种修整过程的附带优点是减少了光致抗蚀剂线的边缘粗糙度并且去除了线脚。

公开(公告)号：US07241674B2

公开(公告)日：2007-07-10

申请号：US10846278

申请日：2004-05-13

申请人： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

IPC分类号： H01L21/3205 ,  H01L21/336

CPC分类号： H01L29/66507 ,  H01L21/28097

摘要： A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

摘要翻译： 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。

公开(公告)号：US20070148881A1

公开(公告)日：2007-06-28

申请号：US11320221

申请日：2005-12-28

申请人： Kai-Ting Tseng ,  Yu-Lien Huang ,  Hao-Ming Lien ,  Ling-Yen Yeh ,  Hun-Jan Tao

发明人： Kai-Ting Tseng ,  Yu-Lien Huang ,  Hao-Ming Lien ,  Ling-Yen Yeh ,  Hun-Jan Tao

IPC分类号： H01L21/336

CPC分类号： H01L21/823878 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/7846

摘要： A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectric material in the first and the second device regions wherein the STI regions define a first active region in the first device region and a second active region in the second device region, forming an insulation mask over the STI region and the first active region in the first device region wherein the insulation mask does not extend over the second device region, and performing a stress-tuning treatment to the semiconductor substrate. The first active region and second active region have tensile stress and compressive stress respectively. An NMOS and a PMOS device are formed on the first and second active regions, respectively.

公开(公告)号：US07217663B2

公开(公告)日：2007-05-15

申请号：US11039043

申请日：2005-01-18

申请人： Yi-Chen Huang ,  Chien Chung Fu ,  Ming-Hong Hsieh ,  Hui Ouyang ,  Yi-Nien Su ,  Hun-Jan Tao

发明人： Yi-Chen Huang ,  Chien Chung Fu ,  Ming-Hong Hsieh ,  Hui Ouyang ,  Yi-Nien Su ,  Hun-Jan Tao

IPC分类号： H01L21/302

CPC分类号： H01L21/76865 ,  H01L21/76808 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76862

摘要： Via hole and trench structures and fabrication methods are disclosed. The structure comprises a conductive layer in a dielectric layer, and a via hole in the dielectric layer for exposing a portion of a surface of the conductive layer. A conductive liner covers the exposed surface of the first conductive layer. A trench is formed on the via hole in the dielectric without the conductive liner layer in the trench. Dual damascene structures and fabrications methods are also disclosed. Following the fabrication methods of the via hole and trench structures, a conductive layer is further formed in the via hole and trench structures.

摘要翻译： 公开了通孔和沟槽结构和制造方法。 该结构包括在电介质层中的导电层和用于暴露导电层表面的一部分的电介质层中的通孔。 导电衬套覆盖第一导电层的暴露表面。 在电介质的通孔上形成沟槽，而沟槽中没有导电衬垫层。 还披露了双镶嵌结构和制造方法。 按照通孔和沟槽结构的制造方法，在通孔和沟槽结构中进一步形成导电层。

公开(公告)号：US20060180854A1

公开(公告)日：2006-08-17

申请号：US11057423

申请日：2005-02-14

申请人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Hun-Jan Tao ,  Chang-Yun Chang ,  Zhong Xuan ,  Sheng-Da Liu

发明人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Hun-Jan Tao ,  Chang-Yun Chang ,  Zhong Xuan ,  Sheng-Da Liu

IPC分类号： H01L31/113

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78687

摘要： A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said sidewall portions comprising major inner and outer surfaces and an upper surface; wherein, each of said surfaces comprises a surface for forming an overlying field effect transistor (FET).

摘要翻译： 一种用于形成多达6个FET器件的多栅极区域FET器件及其形成方法，该器件包括多个鳍状结构，其包括设置在衬底上的半导体材料; 所述多个鳍状结构包括基本上平行的间隔开的侧壁部分，每个所述侧壁部分包括主要内表面和外表面以及上表面; 其中，每个所述表面包括用于形成上覆场效应晶体管（FET）的表面。

公开(公告)号：US07029992B2

公开(公告)日：2006-04-18

申请号：US10920099

申请日：2004-08-17

申请人： Jyu-Horng Shieh ,  Yi-Nien Su ,  Jang-Shiang Tsai ,  Chen-Nan Yeh ,  Hun-Jan Tao

发明人： Jyu-Horng Shieh ,  Yi-Nien Su ,  Jang-Shiang Tsai ,  Chen-Nan Yeh ,  Hun-Jan Tao

IPC分类号： H01L21/322

CPC分类号： H01L21/31138 ,  G03F7/427

摘要： A plasma containing 5–10% oxygen and 90–95% of an inert gas strips photoresist from over a low-k dielectric material formed on or in a semiconductor device. The inert gas may be nitrogen, hydrogen, or a combination thereof, or it may include at least one of nitrogen, hydrogen, NH3, Ar, He, and CF4. The operating pressure of the plasma may range from 1 millitorr to 150 millitor. The plasma removes photoresist, the hard skin formed on photoresist during aggressive etch processes, and polymeric depositions formed during etch processes. The plasma strips photoresist at a rate sufficiently high for production use and does not appreciably attack carbon-containing low-k dielectric materials. An apparatus including a plasma tool containing a semiconductor substrate and the low oxygen-content plasma, is also provided.

摘要翻译： 含有5-10％氧气和90-95％惰性气体的等离子体从形成在半导体器件上或半导体器件中的低k电介质材料上剥离光致抗蚀剂。 惰性气体可以是氮气，氢气或它们的组合，或者它可以包括氮气，氢气，NH 3，Ar，He和CF 4中的至少一种。 。 等离子体的工作压力可以在1毫托至150毫升之间。 等离子体去除光致抗蚀剂，在腐蚀性蚀刻工艺期间在光致抗蚀剂上形成的硬皮以及在蚀刻工艺期间形成的聚合物沉积。 等离子体以足够高的生产用途的速率剥离光致抗蚀剂，并且不会明显地攻击含碳低k电介质材料。 还提供了包括含有半导体衬底和低含氧等离子体的等离子体工具的装置。