公开(公告)号：US20070222000A1

公开(公告)日：2007-09-27

申请号：US11756131

申请日：2007-05-31

Applicant: Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

Inventor： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

IPC: H01L27/088

CPC classification number: H01L29/66507 ,  H01L21/28097

Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

Abstract translation: 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。

公开(公告)号：US07241674B2

公开(公告)日：2007-07-10

申请号：US10846278

申请日：2004-05-13

Applicant: Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

Inventor： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

IPC: H01L21/3205 ,  H01L21/336

CPC classification number: H01L29/66507 ,  H01L21/28097

Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

Abstract translation: 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。

公开(公告)号：US20050253204A1

公开(公告)日：2005-11-17

申请号：US10846278

申请日：2004-05-13

Applicant: Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

Inventor： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/44 ,  H01L29/40

CPC classification number: H01L29/66507 ,  H01L21/28097

Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

Abstract translation: 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。

公开(公告)号：US07271448B2

公开(公告)日：2007-09-18

申请号：US11057423

申请日：2005-02-14

Applicant: Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Hun-Jan Tao ,  Chang-Yun Chang ,  Zhong Tang Xuan ,  Sheng-Da Liu

Inventor： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Hun-Jan Tao ,  Chang-Yun Chang ,  Zhong Tang Xuan ,  Sheng-Da Liu

IPC: H01L29/94

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/78687

Abstract: A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said sidewall portions comprising major inner and outer surfaces and an upper surface; wherein, each of said surfaces comprises a surface for forming an overlying field effect transistor (FET).

Abstract translation: 一种用于形成多达6个FET器件的多栅极区域FET器件及其形成方法，该器件包括多个鳍状结构，其包括设置在衬底上的半导体材料; 所述多个鳍状结构包括基本上平行的间隔开的侧壁部分，每个所述侧壁部分包括主要内表面和外表面以及上表面; 其中，每个所述表面包括用于形成上覆场效应晶体管（FET）的表面。

公开(公告)号：US20070001306A1

公开(公告)日：2007-01-04

申请号：US11172442

申请日：2005-06-30

Applicant: Yi-Nien Su ,  Jyu-Horng Shieh ,  Hun-Jan Tao

Inventor： Yi-Nien Su ,  Jyu-Horng Shieh ,  Hun-Jan Tao

IPC: H01L23/52

CPC classification number: H01L21/76829 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835

Abstract: A semiconductor device. A diffusion barrier layer overlies a substrate. An adhesion promoting layer overlies the diffusion barrier layer. A first dielectric layer between the diffusion barrier layer and the adhesion promoting layer comprises at least one via opening through the diffusion barrier layer and the adhesion promoting layer. A second dielectric layer overlies the adhesion promoting layer, comprising a trench opening above the via opening. A metal interconnect fills the via and trench openings.

Abstract translation: 半导体器件。 扩散阻挡层覆盖在基底上。 粘附促进层覆盖在扩散阻挡层上。 扩散阻挡层和增粘层之间的第一电介质层包括穿过扩散阻挡层和粘合促进层的至少一个通孔。 第二电介质层覆盖粘附促进层，包括在通孔开口上方的沟槽开口。 金属互连件填充通孔和沟槽开口。

公开(公告)号：US07598176B2

公开(公告)日：2009-10-06

申请号：US10949128

申请日：2004-09-23

Applicant: Jang-Shiang Tsai ,  Yi-Nien Su ,  Chung-Chi Ko ,  Jyu-Horng Shieh ,  Peng-Fu Hsu ,  Hun-Jan Tao

Inventor： Jang-Shiang Tsai ,  Yi-Nien Su ,  Chung-Chi Ko ,  Jyu-Horng Shieh ,  Peng-Fu Hsu ,  Hun-Jan Tao

IPC: H01L21/311

CPC classification number: H01L21/02063 ,  G03F7/427 ,  Y10S438/958

Abstract: A plasma processing operation uses a gas mixture of N2 and H2 to both remove a photoresist film and treat a low-k dielectric material. The plasma processing operation prevents degradation of the low-k material by forming a protective layer on the low-k dielectric material. Carbon from the photoresist layer is activated and caused to complex with the low-k dielectric, maintaining a suitably high carbon content and a suitably low dielectric constant. The plasma processing operation uses a gas mixture with H2 constituting at least 10%, by volume, of the gas mixture.

Abstract translation: 等离子体处理操作使用N 2和H 2的气体混合物来去除光致抗蚀剂膜并处理低k电介质材料。 等离子体处理操作通过在低k电介质材料上形成保护层来防止低k材料的劣化。 来自光致抗蚀剂层的碳被激活并与低k电介质复合，保持适当高的碳含量和合适的低介电常数。 等离子体处理操作使用具有构成气体混合物的至少10体积％的H 2的气体混合物。

公开(公告)号：US07208331B2

公开(公告)日：2007-04-24

申请号：US10949037

申请日：2004-09-24

Applicant: Jyu-Horng Shieh ,  Wen-Chih Chiou ,  Peng-Fu Hsu ,  Baw-Ching Perng ,  Hun-Jan Tao ,  Chia-Jen Chen

Inventor： Jyu-Horng Shieh ,  Wen-Chih Chiou ,  Peng-Fu Hsu ,  Baw-Ching Perng ,  Hun-Jan Tao ,  Chia-Jen Chen

IPC: H01L21/66 ,  H01L23/58

CPC classification number: H01L22/34

Abstract: Methods and structures for critical dimension or profile measurement are disclosed. The method provides a substrate having periodic openings therein. Material layers are formed in the openings, substantially planarizing a surface of the substrate. A scattering method is applied to the substrate with the material layers for critical dimension (CD) or profile measurement.

Abstract translation: 公开了关键尺寸或轮廓测量的方法和结构。 该方法提供其中具有周期性开口的基板。 在开口中形成材料层，基本上平坦化基底的表面。 将散射方法应用于具有临界尺寸（CD）或轮廓测量的材料层的基底。

公开(公告)号：US07074727B2

公开(公告)日：2006-07-11

申请号：US10615628

申请日：2003-07-09

Applicant: Peng-Fu Hsu ,  Jyu-Horng Shieh ,  Yung-Cheng Lu ,  Hun-Jan Tao ,  Yuan-Hung Chiu

Inventor： Peng-Fu Hsu ,  Jyu-Horng Shieh ,  Yung-Cheng Lu ,  Hun-Jan Tao ,  Yuan-Hung Chiu

IPC: C08G77/00 ,  H01L21/768

CPC classification number: C08G77/38

Abstract: Low-k organosilicate dielectric material can be exposed to a series of reagents, including a halogenation reagent, an alkylation reagent, and a termination reagent, in order to reverse degradation of dielectric properties caused by previous processing steps.

Abstract translation: 低k有机硅酸盐电介质材料可以暴露于一系列试剂，包括卤化试剂，烷基化试剂和终止试剂，以反转由以前的处理步骤引起的介电性质的退化。

公开(公告)号：US20060154478A1

公开(公告)日：2006-07-13

申请号：US11035325

申请日：2005-01-12

Applicant: Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Nien Su ,  Peng-Fu Hsu ,  Hun-Jan Tao

Inventor： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Nien Su ,  Peng-Fu Hsu ,  Hun-Jan Tao

IPC: H01L21/4763

CPC classification number: H01L21/76802 ,  H01L21/76835

Abstract: Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.

Abstract translation: 公开了形成接触孔结构的方法和结构。 这些方法首先在衬底上形成基本上无硅的材料层。 在基本无硅材料层上形成材料层。 在基本无硅的材料层和材料层内形成接触孔，而基本上不损坏衬底。 此外，在接触孔中形成导电层以形成接触结构。

公开(公告)号：US20060040474A1

公开(公告)日：2006-02-23

申请号：US10920099

申请日：2004-08-17

Applicant: Jyu-Horng Shieh ,  Yi-Nien Su ,  Jang-Shiang Tsai ,  Chen-Nan Yeh ,  Hun-Jan Tao

Inventor： Jyu-Horng Shieh ,  Yi-Nien Su ,  Jang-Shiang Tsai ,  Chen-Nan Yeh ,  Hun-Jan Tao

IPC: H01L21/322

CPC classification number: H01L21/31138 ,  G03F7/427

Abstract: A plasma containing 5-10% oxygen and 90-95% of an inert gas strips photoresist from over a low-k dielectric material formed on or in a semiconductor device. The inert gas may be nitrogen, hydrogen, or a combination thereof, or it may include at least one of nitrogen, hydrogen, NH3, Ar, He, and CF4. The operating pressure of the plasma may range from 1 millitorr to 150 millitor. The plasma removes photoresist, the hard skin formed on photoresist during aggressive etch processes, and polymeric depositions formed during etch processes. The plasma strips photoresist at a rate sufficiently high for production use and does not appreciably attack carbon-containing low-k dielectric materials. An apparatus including a plasma tool containing a semiconductor substrate and the low oxygen-content plasma, is also provided.

Abstract translation: 含有5-10％氧气和90-95％惰性气体的等离子体从形成在半导体器件上或半导体器件中的低k电介质材料上剥离光致抗蚀剂。 惰性气体可以是氮气，氢气或它们的组合，或者它可以包括氮气，氢气，NH 3，Ar，He和CF 4中的至少一种。 。 等离子体的工作压力可以在1毫托至150毫升之间。 等离子体去除光致抗蚀剂，在腐蚀性蚀刻工艺期间在光致抗蚀剂上形成的硬皮以及在蚀刻工艺期间形成的聚合物沉积。 等离子体以足够高的生产用途的速率剥离光致抗蚀剂，并且不会明显地攻击含碳低k电介质材料。 还提供了包括含有半导体衬底和低含氧等离子体的等离子体工具的装置。