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83 条记录 (耗时 0.038 秒)

    ESD protection structure for I/O pad subject to both positive and negative voltages
    72.
    发明授权
    ESD protection structure for I/O pad subject to both positive and negative voltages 有权
    I / O焊盘的ESD保护结构受到正和负电压的影响

    公开(公告)号：US07446378B2

    公开(公告)日：2008-11-04

    申请号：US11027788

    申请日：2004-12-29

    申请人： Gregory Bakker

    发明人： Gregory Bakker

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0266

    摘要： An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive and a second switch connects the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative. A third switch connects the gate of the n-channel MOS transistor to the p-well if it is turned off and a fourth switch connects the gate of the n-channel MOS transistor to VCC if it is turned on.

    摘要翻译： 公开了一种ESD保护电路，用于形成在三阱工艺的内部p阱中的n沟道MOS晶体管，并连接到根据本发明可以经历正和负电压的I / O焊盘。 如果I / O焊盘的电压为正，则第一开关将包含n沟道MOS晶体管的p阱连接到地，而第二开关将包含n沟道MOS晶体管的p阱连接到I / O焊盘 如果I / O焊盘的电压为负。 第三开关将n沟道MOS晶体管的栅极连接到p阱，如果它是截止的，第四个开关将n沟道MOS晶体管的栅极连接到V CC CC 打开。

    CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
    77.
    发明申请
    CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP 有权
    基于可编程逻辑的芯片系统的时钟发生器架构

    公开(公告)号：US20080030235A1

    公开(公告)日：2008-02-07

    申请号：US11871741

    申请日：2007-10-12

    申请人： Shin-Nan Sun ,  Limin Zhu ,  Theodore Speers ,  Gregory Bakker

    发明人： Shin-Nan Sun ,  Limin Zhu ,  Theodore Speers ,  Gregory Bakker

    IPC分类号： H03D9/00

    CPC分类号： H03K19/17732

    摘要： A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

    摘要翻译： 一种可编程片上系统集成电路器件，包括晶体振荡器电路，RC振荡器电路和外部振荡器输入中的至少一个。 时钟调理电路选择性地耦合到可编程逻辑块，晶体振荡器电路，RC振荡器电路和外部振荡器输入之一。 实时时钟可选择性地耦合到可编程逻辑块，晶体振荡器电路，RC振荡器电路和外部振荡器输入之一。 可编程逻辑块耦合到时钟调节电路和实时时钟。

    POWER-UP AND POWER-DOWN CIRCUIT FOR SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT
    78.
    发明申请
    POWER-UP AND POWER-DOWN CIRCUIT FOR SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT 有权
    用于系统级芯片集成电路的上电和掉电电路

    公开(公告)号：US20060284324A1

    公开(公告)日：2006-12-21

    申请号：US11467279

    申请日：2006-08-25

    申请人： Gregory Bakker

    发明人： Gregory Bakker

    IPC分类号： H01L23/52

    CPC分类号： G11C5/147 ,  H01L2924/0002 ,  H03K17/22 ,  Y10T307/50 ,  Y10T307/724 ,  H01L2924/00

    摘要： A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to the first I/O pad. A second I/O pad is coupled internally to an output of the voltage regulator configured to drive the base of an external transistor. A third I/O pad of the integrated circuit is coupled internally to a reference-voltage input of the voltage regulator. A fourth I/O pad is coupled to a feedback input of the voltage regulator. A fifth I/O pad of the integrated circuit is coupled internally to logic circuitry that controls power-up and power down of the integrated circuit from internal signals including internal signals from a real-time clock circuit disposed on the integrated circuit.

    摘要翻译： 用于集成电路的上电和掉电电路包括用于第一电压的电压调节器。 第一个I / O焊盘内部耦合到电压调节器和第一个内部电路的输入端。 第二电压外部耦合到第一I / O焊盘。 第二I / O焊盘内部耦合到被配置为驱动外部晶体管的基极的电压调节器的输出端。 集成电路的第三个I / O焊盘内部耦合到电压调节器的参考电压输入端。 第四I / O焊盘耦合到电压调节器的反馈输入端。 集成电路的第五个I / O焊盘内部耦合到逻辑电路，该逻辑电路从包括设置在集成电路上的实时时钟电路的内部信号的内部信号控制集成电路的上电和掉电。