公开(公告)号：US20110293020A1

公开(公告)日：2011-12-01

申请号：US13204035

申请日：2011-08-05

申请人： Chong Soon Lim ,  Takahiro Nishi

发明人： Chong Soon Lim ,  Takahiro Nishi

IPC分类号： H04N7/26

CPC分类号： H04N19/188 ,  H04N19/1887 ,  H04N19/44 ,  H04N19/597 ,  H04N19/70

摘要： To provide an image decoding method allowing decoding of a multiview video even when no prefix NAL units are used. The image decoding method includes: parsing NAL units of a base view; decoding an image of the base view; parsing MVC extension parameters of a non-base view; searching whether or not prefix NAL units for a base view are present; either computing MVC extension parameters for the base view when no prefix NAL units are present or parsing the MVC extension parameters of the base view when prefix NAL units for the base view are present; and decoding the non-base view using the MVC extension parameters of the base view and the MVC extension parameters of the non-base view.

公开(公告)号：US20080049832A1

公开(公告)日：2008-02-28

申请号：US11628733

申请日：2005-06-07

申请人： Hidekatsu Ozeki ,  Masayasu Iguchi ,  Takahiro Nishi ,  Hiroaki Toida ,  Hiroto Tomita ,  Akihiko Inoue ,  Takashi Hashimoto

发明人： Hidekatsu Ozeki ,  Masayasu Iguchi ,  Takahiro Nishi ,  Hiroaki Toida ,  Hiroto Tomita ,  Akihiko Inoue ,  Takashi Hashimoto

IPC分类号： H04B1/66

CPC分类号： H04N19/42 ,  H04N19/122 ,  H04N19/60

摘要： An image decoding device and an image encoding device according to the present invention includes an arithmetic unit for performing arithmetic processing, an arithmetic data storage unit for storing an arithmetic result by the arithmetic unit, an input selection unit for selecting whether to read pixel data that is to be inputted to the arithmetic unit from compressed image data or from pixel data stored in the arithmetic data storage unit, and inputting the read pixel data to the arithmetic unit, and an arithmetic control unit for controlling, based on a transform mode used and the number of arithmetic operations in the arithmetic unit, a destination from which the pixel data that is to be inputted to the arithmetic unit by the input selection unit is read as well as a combination of pieces of pixel data targeted for the arithmetic processing by the arithmetic unit and multiplier coefficients for the arithmetic processing, the arithmetic control unit previously defining an arithmetic procedure in each transform mode for each unit executable in one arithmetic operation in the arithmetic unit in association with the number of arithmetic operations.

摘要翻译： 根据本发明的图像解码装置和图像编码装置包括：运算单元，用于进行运算处理;算术数据存储单元，用于存储运算单元的算术结果;输入选择单元，用于选择是否读取像素数据， 从压缩图像数据或从存储在算术数据存储单元中的像素数据输入到运算单元，并将读取的像素数据输入到运算单元，以及运算控制单元，用于基于所使用的变换模式和 算术单元中的算术运算的数量，由输入选择单元输入到运算单元的像素数据的目的地以及由运算单元计算的运算处理对象的像素数据的组合 算术单元和乘法器系数，运算控制单元先前定义算术 在算术单元中的一个算术运算中，每个单元的每个变换模式的过程与算术运算的数量相关联。

公开(公告)号：US20070258702A1

公开(公告)日：2007-11-08

申请号：US10565131

申请日：2005-06-20

申请人： Toshiyasu Sugio ,  Hiroaki Toida ,  Takahiro Nishi ,  Tadamasa Toma ,  Hisao Sasai

发明人： Toshiyasu Sugio ,  Hiroaki Toida ,  Takahiro Nishi ,  Tadamasa Toma ,  Hisao Sasai

IPC分类号： H04N7/26

CPC分类号： H04N9/7921 ,  G06F1/1626 ,  G06F1/1656 ,  G06F1/1686 ,  H04N5/232 ,  H04N5/772 ,  H04N5/781 ,  H04N5/782 ,  H04N5/907 ,  H04N7/012 ,  H04N9/8042 ,  H04N9/8063 ,  H04N9/8205 ,  H04N19/103 ,  H04N19/132 ,  H04N19/156 ,  H04N19/172 ,  H04N19/182 ,  H04N19/40

摘要： An object of the present invention is to provide a recording/reproduction terminal having a general-purpose slot and a detachable encoding or decoding device. A recording/reproduction device includes: a recording/reproduction terminal 103 which records and reproduces signals representing audio or video; and a removable coding device 100 which is detachably connected to the recording/reproduction terminal 103, and the recording/reproduction terminal 103 has a terminal information storage unit 105 which stores terminal information which is information regarding the recording/reproduction terminal 103, and a removable coding device 100 has: a terminal information obtainment unit 101 which obtains the terminal information from the recording/reproduction terminal 103 when the removable coding device 100 is connected to the recording/reproduction terminal 103; and a signal conversion unit 102 which encodes or decodes the signals representing audio or video based on the obtained terminal information.

摘要翻译： 本发明的目的是提供一种具有通用时隙和可拆卸编码或解码装置的记录/再现终端。 记录/再现装置包括：记录和再现表示音频或视频的信号的记录/再现终端103; 以及可拆卸地连接到记录/再现终端103的可移除编码装置100，并且记录/再现终端103具有终端信息存储单元105，其存储关于记录/再现终端103的信息的终端信息，以及可移除 编码装置100具有：终端信息获取单元101，当可移除编码装置100连接到记录/再现终端103时，其从记录/再现终端103获得终端信息; 以及信号转换单元102，其基于获得的终端信息对表示音频或视频的信号进行编码或解码。

公开(公告)号：US20070183508A1

公开(公告)日：2007-08-09

申请号：US10591177

申请日：2005-08-02

申请人： Shintaro Kudo ,  Takahiro Nishi ,  Masayasu Iguchi

发明人： Shintaro Kudo ,  Takahiro Nishi ,  Masayasu Iguchi

IPC分类号： H04N11/02 ,  H04B1/66

CPC分类号： H04N19/86 ,  H04N19/117 ,  H04N19/134 ,  H04N19/174 ,  H04N19/176 ,  H04N19/186 ,  H04N19/61 ,  H04N19/82

摘要： Provided is an image decoding device which can eliminate block distortion and also can restrain decrease of a processing speed, even if an order of decoding blocks is changed. Such an image decoding device (100) has: a variable length decoding unit (111) or the like which sequentially decodes the blocks; a frame memory (102); a de-blocking filtering unit (119) which applies filtering processing to each decoded block; switches (103and 104) in the first executing status, which stores the block into the frame memory (102) every time the block is decoded, and applies the filtering processing to the stored blocks; switches (103 and 104) in the second executing status, which applies the filtering processing to the block to be applied with the filtering processing every time the block is decoded; and a control unit (101) which switches between the first executing status and the second executing status of the switches (103 and 104).

摘要翻译： 提供了一种能够消除块失真的图像解码装置，并且即使改变解码块的顺序，也可以抑制处理速度的降低。 这种图像解码装置（100）具有：对块进行顺序解码的可变长度解码部（111）等; 帧存储器（102）; 对每个解码块应用滤波处理的解块滤波单元（119）; 开关（103和104）处于第一执行状态，每当该块解码时将该块存储到帧存储器（102）中，并将该过滤处理应用于存储的块; 在第二执行状态下的开关（103和104），每当该块被解码时，将过滤处理应用于要被应用于滤波处理的块; 以及在开关（103和104）的第一执行状态和第二执行状态之间切换的控制单元（101）。

公开(公告)号：US06947659B2

公开(公告)日：2005-09-20

申请号：US10751476

申请日：2004-01-06

申请人： Takahiro Nishi ,  Shinya Kadono ,  Choong Seng Boon

发明人： Takahiro Nishi ,  Shinya Kadono ,  Choong Seng Boon

IPC分类号： H04N5/92 ,  G06T9/00 ,  H04N7/08 ,  H04N7/081 ,  H04N7/24 ,  H04N7/50 ,  H04N7/52 ,  H04N19/00 ,  H04N19/46 ,  H04N19/503 ,  H04N19/70 ,  H04N19/85 ,  H04N21/2343 ,  H04N21/235 ,  H04N21/236 ,  H04N21/242 ,  H04N21/43 ,  H04N21/434 ,  H04N21/435 ,  H04N21/6332 ,  H04N21/654 ,  H06N5/91 ,  H04N5/91

CPC分类号： H04N7/52 ,  H04N19/46 ,  H04N21/234318 ,  H04N21/235 ,  H04N21/23614 ,  H04N21/242 ,  H04N21/4307 ,  H04N21/4348 ,  H04N21/435 ,  H04N21/6332 ,  H04N21/654

摘要： A data structure of an image signal includes a reproduction cycle identifier indicating whether the cycle of image display for each frame is variable or not. When the display cycle identifier indicates that the display cycle is fixed, display cycle data is inserted in a header of the coded image data, and data relating to the frame number is inserted in each frame. On the other hand, when the display cycle identifier indicates that the display cycle is variable, display time data is inserted for each frame. Therefore, when decoding and displaying the coded image data having a fixed display cycle, the decoded image data can be displayed by a simple circuit structure, i.e., based on the display cycle data and the frame number data having a relatively small data quantity (bit number), without referring to the display time data having a relatively large data quantity for each frame. Furthermore, this data structure can be applied to a coded image signal having a variable display cycle.

摘要翻译： 图像信号的数据结构包括指示每帧的图像显示周期是否可变的再现周期标识符。 当显示周期标识符指示显示周期固定时，将显示周期数据插入编码图像数据的标题中，并且在每帧中插入与帧号相关的数据。 另一方面，当显示周期标识符指示显示周期是可变的时，针对每个帧插入显示时间数据。 因此，当解码和显示具有固定显示周期的编码图像数据时，解码图像数据可以通过简单的电路结构显示，即，基于显示周期数据和具有相对较小数据量的位数（bit 数字），而不参考每帧具有相对较大数据量的显示时间数据。 此外，该数据结构可以应用于具有可变显示周期的编码图像信号。

公开(公告)号：US06654541B1

公开(公告)日：2003-11-25

申请号：US09176953

申请日：1998-10-22

申请人： Takahiro Nishi ,  Shinya Kadono ,  Choong Seng Boon

发明人： Takahiro Nishi ,  Shinya Kadono ,  Choong Seng Boon

IPC分类号： H04N591

CPC分类号： H04N7/52 ,  H04N19/46 ,  H04N21/234318 ,  H04N21/235 ,  H04N21/23614 ,  H04N21/242 ,  H04N21/4307 ,  H04N21/4348 ,  H04N21/435 ,  H04N21/6332 ,  H04N21/654

摘要： A data structure of an image signal includes a reproduction cycle identifier indicating whether the cycle of image display for each frame is variable or not. When the display cycle identifier indicates that the display cycle is fixed, display cycle data is inserted in a header of the coded image data, and data relating to the frame number is inserted in each frame. On the other hand, when the display cycle identifier indicates that the display cycle is variable, display time data is inserted for each frame. Therefore, when decoding and displaying the coded image data having a fixed display cycle, the decoded image data can be displayed by a simple circuit structure, i.e., based on the display cycle data and the frame number data having a relatively small data quantity (bit number), without referring to the display time data having a relatively large data quantity for each frame. Furthermore, this data structure can be applied to a coded image signal having a variable display cycle.

摘要翻译： 图像信号的数据结构包括指示每帧的图像显示周期是否可变的再现周期标识符。 当显示周期标识符指示显示周期固定时，将显示周期数据插入编码图像数据的标题中，并且在每帧中插入与帧号相关的数据。 另一方面，当显示周期标识符指示显示周期是可变的时，针对每个帧插入显示时间数据。 因此，当解码和显示具有固定显示周期的编码图像数据时，解码图像数据可以通过简单的电路结构显示，即，基于显示周期数据和具有相对较小数据量的位数（bit 数字），而不参考每帧具有相对较大数据量的显示时间数据。 此外，该数据结构可以应用于具有可变显示周期的编码图像信号。

公开(公告)号：US06574368B1

公开(公告)日：2003-06-03

申请号：US09547883

申请日：2000-04-12

申请人： Choong Seng Boon ,  Takahiro Nishi

发明人： Choong Seng Boon ,  Takahiro Nishi

IPC分类号： G06K936

CPC分类号： H04N21/23655 ,  H04N19/115 ,  H04N19/12 ,  H04N19/126 ,  H04N19/14 ,  H04N19/15 ,  H04N19/152 ,  H04N19/17 ,  H04N19/172 ,  H04N19/20 ,  H04N19/61

摘要： The present invention provides an image processing apparatus which can perform a coding processing for object image data of each constituent on optimal conditions, thereby increasing the quality of a whole reproduced image of a video signal reproduced. The image processing apparatus comprises a decision unit 210 for deciding the number of bits per frame which are allocated to a video signal corresponding to a target frame as a target of the coding processing and an a decision unit 209 for allocating the number of bits per frame to each constituent according to complexity of each of constituents of the target frame, and codes each of the object image data corresponding to the target frame on the basis of the number of bits distributed to each constituent.

摘要翻译： 本发明提供一种图像处理装置，其可以对最佳条件下的每个成分的对象图像数据执行编码处理，从而提高再现的视频信号的整个再现图像的质量。 图像处理装置包括：决定单元210，用于确定分配给与目标帧相对应的视频信号的每帧的比特数作为编码处理的目标;以及判定单元209，用于分配每帧的比特数 根据目标帧的每个组成部分的复杂度，根据分配给每个组成部分的比特数，对与目标帧对应的目标图像数据进行编码。

公开(公告)号：US06549724B2

公开(公告)日：2003-04-15

申请号：US09824711

申请日：2001-04-04

申请人： Takahiro Nishi ,  Shinya Kadono ,  Choong Seng Boon

发明人： Takahiro Nishi ,  Shinya Kadono ,  Choong Seng Boon

IPC分类号： H04N726

CPC分类号： H04N7/52 ,  H04N19/46 ,  H04N21/234318 ,  H04N21/235 ,  H04N21/23614 ,  H04N21/242 ,  H04N21/4307 ,  H04N21/4348 ,  H04N21/435 ,  H04N21/6332 ,  H04N21/654

摘要： A data structure of an image signal includes a reproduction cycle identifier indicating whether the cycle of image display for each frame is variable or not. When the display cycle identifier indicates that the display cycle is fixed, display cycle data is inserted in a header of the coded image data, and data relating to the frame number is inserted in each frame. On the other hand, when the display cycle identifier indicates that the display cycle is variable, display time data is inserted for each frame. Therefore, when decoding and displaying the coded image data having a fixed display cycle, the decoded image data can be displayed by a simple circuit structure, i.e., based on the display cycle data and the frame number data having a relatively small data quantity (bit number), without referring to the display time data having a relatively large data quantity for each frame. Furthermore, this data structure can be applied to a coded image signal having a variable display cycle.

公开(公告)号：US06275530B1

公开(公告)日：2001-08-14

申请号：US09091678

申请日：1998-08-11

申请人： Takahiro Nishi ,  Shinya Kadono

发明人： Takahiro Nishi ,  Shinya Kadono

IPC分类号： H04N736

CPC分类号： H04N19/44 ,  H04N19/124 ,  H04N19/15 ,  H04N19/154 ,  H04N19/172 ,  H04N19/176 ,  H04N19/18 ,  H04N19/30

摘要： An image coding apparatus 1 of the present invention comprises a coding controller 112a for generating a transparency coding parameter 121 for controlling coding process for transparency signals on the basis of a pixel value coding parameter 104 for controlling coding process for pixel value signals and performs coding process for transparency signals 102 on the basis of the transparency coding parameter 121. The image coding apparatus 1 above constructed can control an image quality obtained from transparency signals of each image included in a composite image according to an image quality of pixel value signals of each image of the composite image, and thus it is possible to reduce redundant information of coded transparency signals 106 resulting from coding the transparency signals without degrading an image quality of each image, thereby implementing recording and transmission of image signals with fewer bits with no degradation of image quality.

摘要翻译： 本发明的图像编码装置1包括：编码控制器112a，用于根据用于控制像素值信号的编码处理的像素值编码参数104，生成用于控制透过度信号的编码处理的透过度编码参数121，并执行编码处理 根据透过度编码参数121对透过度信号102进行透镜化。上述构成的图像编码装置1可以根据各图像的像素值信号的图像质量来控制从包含在合成图像中的各图像的透过度信号得到的图像质量 的复合图像，因此可以减少由透明度信号编码而产生的透过度信号106的冗余信息，而不降低每个图像的图像质量，从而实现具有较少位的图像信号的记录和传输，而不会降低图像 质量。

公开(公告)号：US10439637B2

公开(公告)日：2019-10-08

申请号：US13535414

申请日：2012-06-28

申请人： Hisao Sasai ,  Takahiro Nishi ,  Youji Shibahara ,  Toshiyasu Sugio ,  Kyoko Tanikawa ,  Toru Matsunobu

发明人： Hisao Sasai ,  Takahiro Nishi ,  Youji Shibahara ,  Toshiyasu Sugio ,  Kyoko Tanikawa ,  Toru Matsunobu

IPC分类号： H04N19/13 ,  H03M7/40 ,  H04N19/186

摘要： The image decoding method includes: determining a context for use in a current block to be processed, from among a plurality of contexts; and performing arithmetic decoding on a bit sequence corresponding to the current block, using the determined context, wherein in the determining: the context is determined under a condition that control parameters of neighboring blocks of the current block are used, when the signal type is a first type, the neighboring blocks being a left block and an upper block of the current block; and the context is determined under a condition that the control parameter of the upper block is not used, when the signal type is a second type, and the second type is one of “cbf_luma”, “cbf_cb”, and “cbf_cr”.