公开(公告)号：US07303950B2

公开(公告)日：2007-12-04

申请号：US11034938

申请日：2005-01-14

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下面形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US07183167B2

公开(公告)日：2007-02-27

申请号：US11011655

申请日：2004-12-15

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

IPC分类号： H01L21/336

CPC分类号： H01L21/2652 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

公开(公告)号：US20060267012A1

公开(公告)日：2006-11-30

申请号：US11498800

申请日：2006-08-04

申请人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

发明人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

IPC分类号： H01L31/00

CPC分类号： H01L29/78609 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78639

摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.

公开(公告)号：US20060134843A1

公开(公告)日：2006-06-22

申请号：US11317687

申请日：2005-12-27

申请人： Shigenobu Maeda ,  Takuji Matsumoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Takuji Matsumoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7841 ,  H01L29/78615 ,  H01L29/78654 ,  Y10S438/981

摘要： It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.

摘要翻译： 本发明的目的是提供一种能够进行身体固定并实现快速且稳定的操作的SOI装置。 在栅极（12）的栅极接触焊盘（GP）与SOI层（3）之间的部分之间设置厚度为1〜5nm的栅极绝缘膜（11）和栅极绝缘膜（ 在栅极接触焊盘（GP）和SOI层（3）之间设置有厚度为5〜15nm的光栅（110）。 连续设置栅极绝缘膜（11）和栅极绝缘膜（110）。

公开(公告)号：US20050275021A1

公开(公告)日：2005-12-15

申请号：US11197397

申请日：2005-08-05

申请人： Takuji Matsumoto ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

发明人： Takuji Matsumoto ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

IPC分类号： H01L21/762 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66545 ,  H01L21/28052 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7845

摘要： A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.

摘要翻译： 提供一种半导体器件及其制造方法，其可以适当地避免隔离击穿电压的降低，而不会引起诸如结电容增加的不利影响。 在通过形成凹部（14）使硅层（3）变薄之后形成杂质导入区域（11）。 因此，在位于元件隔离绝缘膜（5）的底部和BOX层（2）的上表面之间的p型硅层（3）的部分中不会注入n型杂质，避免了还原 的隔离击穿电压。 此外，由于杂质引入区域（11）形成为到达BOX层（2）的上表面，所以源极/漏极区域（12）的结电容不增加。

公开(公告)号：US20050133864A1

公开(公告)日：2005-06-23

申请号：US11002142

申请日：2004-12-03

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L27/13 ,  H01L29/786 ,  H01L21/00 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L27/0617 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/10 ,  H01L28/20 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： Plural trench isolation films (4) are provided with portions of an SOI layer (3) interposed therebetween in a surface of the SOI layer (3) in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element (30) are formed on the trench isolation films (4), respectively. Each of the trench isolation films (4) includes a central portion which passes through the SOI layer (3) and reaches a buried oxide film (2) to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer (3) and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films (4) includes a hybrid-trench isolation structure.

摘要翻译： 多个沟槽隔离膜（4）在其中设置有螺旋电感器（SI）的电阻器区域（RR）中的SOI层（3）的表面中设置有SOI层（3）的部分。 电阻元件（30）分别形成在沟槽隔离膜（4）上。 每个沟槽隔离膜（4）包括通过SOI层（3）并到达掩埋氧化膜（2）以包括全沟槽隔离结构的中心部分，并且每个沟道隔离膜仅穿过 SOI层（3）的一部分并且位于SOI层3上以包括部分沟槽隔离结构。 因此，每个沟槽隔离膜（4）包括混合沟槽隔离结构。

公开(公告)号：US06864534B2

公开(公告)日：2005-03-08

申请号：US09930202

申请日：2001-08-16

申请人： Takashi Ipposhi ,  Takuji Matsumoto

发明人： Takashi Ipposhi ,  Takuji Matsumoto

IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L21/336 ,  H01L21/762 ,  H01L23/544 ,  H01L29/04 ,  H01L29/786 ,  H01L27/01 ,  H01L29/00

CPC分类号： H01L23/544 ,  H01L21/76254 ,  H01L29/045 ,  H01L2223/54406 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor wafer having crystal orientations of a wafer for the support substrate and a wafer for the device formation shifted from each other, wherein two kinds of wafers having different crystal orientations in which a notch or an orientation flat is to be provided do not need to be prepared. One of two semiconductor wafers having a notch or an orientation flat provided in the same crystal orientation is set to be a wafer (1) for the support substrate and the other is set to be a wafer for the device formation. Both wafers are bonded with the notches or orientation flats shifted from each other (for example, a crystal orientation of the wafer for the device formation and the crystal orientation of the wafer (1) for the support substrate are set to the same direction). The wafer for the device formation is divided to obtain an SOI layer (3). A MOS transistor (TR1) or the like is formed on the SOI layer (3).

摘要翻译： 为了提供具有用于支撑基板的晶片的晶体取向和用于器件形成的晶片彼此偏移的半导体晶片，其中将提供具有不同晶体取向的两种晶片（其中将提供缺口或取向平面）不是 需要准备 将具有以相同晶体取向<110>提供的凹口或取向平面的两个半导体晶片中的一个设置为用于支撑衬底的晶片（1），另一个被设置为用于器件形成的晶片。 两个晶片与凹槽或取向平面彼此偏移（例如，用于器件形成的晶片的晶体取向<100>和用于支撑衬底的晶片（1）的晶体取向<110>被结合 朝同一个方向）。 用于器件形成的晶片被分割以获得SOI层（3）。 在SOI层（3）上形成MOS晶体管（TR1）等。

公开(公告)号：US06541841B2

公开(公告)日：2003-04-01

申请号：US10163613

申请日：2002-06-07

申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： H01L2900

CPC分类号： H01L23/645 ,  H01L21/84 ,  H01L23/522 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/1203 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with a spiral inductor is provided, which determines the area of an insulation layer to be provided in the surface of a wiring board thereunder. A trench isolation oxide film, which is a complete isolation oxide film including in part the structure of a partial isolation oxide film, is provided in a larger area of the surface of an SOI layer than that corresponding to the area of a spiral inductor. The trench isolation oxide film is comprised of a first portion having a first width and extending in a direction approximately perpendicular the surface of a buried oxide film, and a second portion having a second width smaller than the first width and being continuously formed under the first portion, extending approximately perpendicular to the surface of the buried oxide film. The trench isolation oxide film is provided such that a horizontal distance between each end surface of the second portion and a corresponding end surface of the spiral inductor makes a predetermined distance or more.

摘要翻译： 提供具有螺旋电感器的半导体器件，其确定要在其下面的布线板的表面中提供的绝缘层的面积。 在SOI层表面的与螺旋形电感器的面积相对应的面的大面积上，设置有作为部分隔离氧化膜的结构的完全隔离氧化膜的沟槽隔离氧化膜。 沟槽隔离氧化膜由具有第一宽度的第一部分和大致垂直于埋入氧化膜的表面的方向延伸的第一部分和具有小于第一宽度的第二宽度的第二部分构成，并且连续地形成在第一 部分，大致垂直于掩埋氧化膜的表面延伸。 沟槽隔离氧化膜被设置为使得第二部分的每个端表面与螺旋电感器的相应端面之间的水平距离达到预定距离或更大。

公开(公告)号：US06452249B1

公开(公告)日：2002-09-17

申请号：US09688812

申请日：2000-10-17

申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Yuuichi Hirano ,  Takashi Ipposhi ,  Takuji Matsumoto

发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Yuuichi Hirano ,  Takashi Ipposhi ,  Takuji Matsumoto

IPC分类号： H01L2900

CPC分类号： H01L23/5227 ,  H01L21/28518 ,  H01L21/84 ,  H01L23/645 ,  H01L27/0688 ,  H01L27/08 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having an inductor is provided. In an RF circuit portion (RP), a region in an SOI layer (3) corresponding to a region in which a spiral inductor (SI) is provided is divided into a plurality of SOI regions (21) by a plurality of trench isolation oxide films (11). The trench isolation oxide films (11) are formed by filling trenches extending from the surface of the SOI layer (3) to the surface of a buried oxide film (2) with a silicon oxide film, and completely electrically isolate the SOI regions (21) from each other. The trench isolation oxide films (11) have a predetermined width and are shaped to extend substantially perpendicularly to the surface of the buried oxide film (2). The semiconductor device is capable of reducing electrostatically induced power dissipation and electromagnetically induced power dissipation, and preventing the structure and manufacturing steps thereof from becoming complicated.

摘要翻译： 提供具有电感器的半导体器件。 在RF电路部分（RP）中，与设置有螺旋电感器（SI）的区域对应的SOI层（3）中的区域被多个沟槽隔离氧化物（21）分成多个SOI区域 电影（11）。 沟槽隔离氧化膜（11）通过用氧化硅膜填充从SOI层（3）的表面延伸到掩埋氧化膜（2）的表面的沟槽而形成，并将SOI区域（21 ）彼此。 沟槽隔离氧化物膜（11）具有预定的宽度并且被成形为基本上垂直于掩埋氧化膜（2）的表面延伸。 半导体器件能够降低静电感应功率耗散和电磁感应功率消耗，并且防止其结构和制造步骤变得复杂。

公开(公告)号：US06426543B1

公开(公告)日：2002-07-30

申请号：US09717038

申请日：2000-11-22

申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： H01L2900

CPC分类号： H01L23/645 ,  H01L21/84 ,  H01L23/522 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/1203 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with a spiral inductor is provided, which determines the area of an insulation layer to be provided in the surface of a wiring board thereunder. A trench isolation oxide film, which is a complete isolation oxide film including in part the structure of a partial isolation oxide film, is provided in a larger area of the surface of an SOI layer than that corresponding to the area of a spiral inductor. The trench isolation oxide film includes a first portion having a first width and extending in a direction approximately perpendicular the surface of a buried oxide film, and a second portion having a second width smaller than the first width and being continuously formed under the first portion, extending approximately perpendicular to the surface of the buried oxide film. The trench isolation oxide film is provided such that a horizontal distance between each end surface of the second portion and a corresponding end surface of the spiral inductor makes a predetermined distance or more.

摘要翻译： 提供具有螺旋电感器的半导体器件，其确定要在其下面的布线板的表面中提供的绝缘层的面积。 在SOI层表面的与螺旋形电感器的面积相对应的面的大面积上，设置有作为部分隔离氧化膜的结构的完全隔离氧化膜的沟槽隔离氧化膜。 沟槽隔离氧化膜包括具有第一宽度并且在大致垂直于掩埋氧化膜的表面的方向上延伸的第一部分和具有小于第一宽度的第二宽度的第二部分并且连续地形成在第一部分下方， 大致垂直于埋入氧化膜的表面延伸。 沟槽隔离氧化膜被设置为使得第二部分的每个端表面与螺旋电感器的相应端面之间的水平距离达到预定距离或更大。