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    Method, apparatus, and system for energy efficiency and energy conservation including balancing power among multi-frequency domains of a processor based on efficiency rating scheme
    71.
    发明授权
    Method, apparatus, and system for energy efficiency and energy conservation including balancing power among multi-frequency domains of a processor based on efficiency rating scheme 有权
    包括基于效率评估方案的处理器的多频域之间的平衡功率的能量效率和节能的方法，装置和系统

    公开(公告)号：US09239611B2

    公开(公告)日：2016-01-19

    申请号：US13311467

    申请日：2011-12-05

    申请人： Seongwoo Kim ,  Jeremy Shrall ,  Jay D. Schwartz ,  Stephen H. Gunther ,  Travis C. Furrer

    发明人： Seongwoo Kim ,  Jeremy Shrall ,  Jay D. Schwartz ,  Stephen H. Gunther ,  Travis C. Furrer

    IPC分类号： G06F11/34 ,  G06F1/32

    CPC分类号： G06F1/329 ,  G06F1/3206 ,  G06F11/3466 ,  Y02D10/24

    摘要： The efficiency rating (ER) of each domain, in a processor, may be compared and then the power budget may be allocated, effectively, among the domains based on the ERs of the domains. The ER may indicate relative advantage among domains in terms of performance return for a given power budget, i.e., a higher effectiveness may be expected in power utilization if the ER is higher for a domain. The ER of a domain may be defined as (scalability factor/cost factor*alpha). The scalability factor may be defined as a performance increase (in %) brought about by an increase in the clock frequency (in %) provided to the domain. The cost factor may be defined as a power budget value required in bringing about an increase in the clock frequency provided to the domain and alpha is an adjustment factor.

    摘要翻译： 可以比较处理器中每个域的效率等级（ER），然后基于域的ER来在域中有效地分配功率预算。 对于给定的功率预算，ER可以指示域之间的性能回报方面的相对优势，即如果ER对于域更高，则在功率利用中可以预期更高的有效性。 域的ER可以定义为（可扩展性因子/成本因子*α）。 可扩展性因素可以被定义为由提供给域的时钟频率（以％计）的增加而导致的性能增加（以％计）。 成本因素可以被定义为使得提供给域的时钟频率增加所需的功率预算值，而α是调整因子。

    Dynamic voltage transitions
    74.
    发明授权
    Dynamic voltage transitions 有权

    公开(公告)号：US08707064B2

    公开(公告)日：2014-04-22

    申请号：US13028028

    申请日：2011-02-15

    申请人： Stephen H. Gunther ,  Robert Greiner ,  Matthew M. Ma ,  Kevin Dai

    发明人： Stephen H. Gunther ,  Robert Greiner ,  Matthew M. Ma ,  Kevin Dai

    IPC分类号： G06F1/26 ,  G06F13/00

    CPC分类号： G06F1/26

    摘要： The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

    Acoustic Noise Mitigation Using Periodicity Disruption
    75.
    发明申请
    Acoustic Noise Mitigation Using Periodicity Disruption 有权
    使用周期性破坏的声学噪声减轻

    公开(公告)号：US20130346764A1

    公开(公告)日：2013-12-26

    申请号：US13532949

    申请日：2012-06-26

    申请人： Jessica Gullbrand ,  Karthik Sankaranaravanan ,  Willem M. Beltman ,  Eric Baugh ,  Stephen H. Gunther ,  Jay D. Schwartz

    发明人： Jessica Gullbrand ,  Karthik Sankaranaravanan ,  Willem M. Beltman ,  Eric Baugh ,  Stephen H. Gunther ,  Jay D. Schwartz

    IPC分类号： G06F1/26

    CPC分类号： H02M1/44 ,  G06F1/3203 ,  H02M1/36

    摘要： In one or more embodiments, a fixed time interval for a system is determined. The fixed time interval corresponds to time between clock ticks. A random time interval is determined based on the fixed time interval and an offset. One or more electronic components affixed to a motherboard are transitioned to a new power state when the random time interval has elapsed. By introducing a randomization to the timing element to a control signal that drives the power state transition, a periodicity for the system is disrupted. The disruption in periodicity mitigates acoustic noise generated by vibrations in electronic components and motherboards affected by current and/or voltage transitions.

    摘要翻译： 在一个或多个实施例中，确定系统的固定时间间隔。 固定时间间隔对应于时钟间隔之间的时间。 基于固定时间间隔和偏移确定随机时间间隔。 当随机时间间隔过去时，固定到母板上的一个或多个电子部件转变到新的电源状态。 通过将定时元件的随机化引入到驱动电源状态转换的控制信号，系统的周期性被破坏。 周期性的破坏减轻了受电流和/或电压转换影响的电子元件和母板振动产生的声音噪声。

    Mechanisms for utilizing efficiency metrics to control embedded dynamic random access memory power states on a semiconductor integrated circuit package
    76.
    发明授权
    Mechanisms for utilizing efficiency metrics to control embedded dynamic random access memory power states on a semiconductor integrated circuit package 有权
    利用效率度量来控制半导体集成电路封装上的嵌入式动态随机存取存储器功率状态的机制

    公开(公告)号：US08611170B2

    公开(公告)日：2013-12-17

    申请号：US13341868

    申请日：2011-12-30

    申请人： Timothy Y. Kam ,  Jay D. Schwartz ,  Seongwoo Kim ,  Stephen H. Gunther

    发明人： Timothy Y. Kam ,  Jay D. Schwartz ,  Seongwoo Kim ,  Stephen H. Gunther

    IPC分类号： G11C5/14

    CPC分类号： G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    摘要： Power management of an embedded dynamic random access memory (eDRAM) using collected performance counter statistics to generating a set of one or more eDRAM effectiveness predictions. Using a set of one or more eDRAM effectiveness thresholds, each corresponding to one of the set of eDRAM effectiveness predictions, to determine whether at least one eDRAM effectiveness prediction has crossed over threshold. In the case that at least one eDRAM effectiveness prediction has crossed over its threshold, transitioning the eDRAM to a new power state. Power management is achieved by transitioning to a power-off state or self-refresh state and reducing the amount of power consumed by the eDRAM as compared to a power-on state.

    摘要翻译： 使用收集的性能计数器统计信息来生成一组或多个eDRAM有效性预测的嵌入式动态随机存取存储器（eDRAM）的电源管理。 使用一组一个或多个eDRAM有效性阈值，每个eDRAM有效性阈值对应于一组eDRAM有效性预测之一，以确定至少一个eDRAM有效性预测是否超过阈值。 在至少一个eDRAM有效性预测超过其阈值的情况下，将eDRAM转换到新的电源状态。 通过转换到断电状态或自刷新状态并减少eDRAM与上电状态相比所消耗的功率量来实现电源管理。

    DYNAMIC VOLTAGE TRANSITIONS
    78.
    发明申请
    DYNAMIC VOLTAGE TRANSITIONS 有权
    动态电压转换

    公开(公告)号：US20120324253A1

    公开(公告)日：2012-12-20

    申请号：US13600044

    申请日：2012-08-30

    申请人： Stephen H. Gunther ,  Robert Greiner ,  Matthew M. Ma ,  Kevin Dai

    发明人： Stephen H. Gunther ,  Robert Greiner ,  Matthew M. Ma ,  Kevin Dai

    IPC分类号： G06F1/26

    CPC分类号： G06F1/26

    摘要： The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

    摘要翻译： 响应于一个或多个条件（例如，膝上型计算机连接到AC电源）来改变集成电路（例如，处理器）的工作电压。 集成电路的工作频率和工作电压均改变。 使得向集成电路提供工作电压的电压调节器使用一个或多个中间步骤在电压电平之间转变。 在新电压和整个电压转换期间，集成电路继续以正常方式工作。