公开(公告)号：US07961167B2

公开(公告)日：2011-06-14

申请号：US11298396

申请日：2005-12-08

申请人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Masaki Murase ,  Yoshihiko Toyoshima ,  Kazuya Nomura ,  Masaaki Tonogai ,  Daisuke Ito

发明人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Masaki Murase ,  Yoshihiko Toyoshima ,  Kazuya Nomura ,  Masaaki Tonogai ,  Daisuke Ito

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297

摘要： A display device and mobile terminal are provided. The display device can narrow the pitch, narrow the frame, and further reduce power consumption. The display device includes a display area; a vertical drive circuit; a first horizontal drive circuit converting input first and second digital image data to analog image signals, and supplying the same to a data line selected by the vertical drive circuit; and a second horizontal drive circuit converting input third digital image data to an analog image signal, and supplying the same to a data line selected by the vertical drive circuit. The first horizontal drive circuit includes a sampling latch circuit, a second latch circuit, a digital/analog conversion circuit, and a line selector for selecting the first and second digital image data in a time division manner in a predetermined period and outputting the same to the data line.

摘要翻译： 提供了显示装置和移动终端。 显示装置可以缩小音调，缩小框架，并进一步降低功耗。 显示装置包括显示区域; 垂直驱动电路; 第一水平驱动电路，将输入的第一和第二数字图像数据转换为模拟图像信号，并将其提供给由垂直驱动电路选择的数据线; 以及第二水平驱动电路，将输入的第三数字图像数据转换为模拟图像信号，并将其提供给由垂直驱动电路选择的数据线。 第一水平驱动电路包括采样锁存电路，第二锁存电路，数字/模拟转换电路和线选择器，用于在预定周期内以时分方式选择第一和第二数字图像数据并将其输出到 数据线。

公开(公告)号：US20100271359A1

公开(公告)日：2010-10-28

申请号：US12760284

申请日：2010-04-14

申请人： Takeya Takeuchi ,  Werapong Jarupoonphol ,  Tomohiko Sato ,  Yoshitoshi Kida

发明人： Takeya Takeuchi ,  Werapong Jarupoonphol ,  Tomohiko Sato ,  Yoshitoshi Kida

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3655 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2320/0209 ,  G09G2330/021

摘要： The present invention provides a liquid crystal display device including: a pixel array including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, a plurality of liquid crystal elements arranged in a matrix corresponding to an intersection of each scanning line and each signal line, and a plurality of common connection lines arranged one by one corresponding to the liquid crystal elements of each line; a scanning line drive circuit; a signal line drive circuit; and a common connection line drive circuit electrically separating, from each other, one or a plurality of common connection lines (first common connection lines), and a plurality of common connection lines (second common connection lines), and electrically connecting the plurality of second common connection lines to each other to independently drive the first common connection line and the second connection lines from each other.

摘要翻译： 本发明提供一种液晶显示装置，包括：像素阵列，包括排列成行的多条扫描线，多列排列的信号线，多个液晶元件排列成与每个扫描的交点相对应的矩阵 线和每个信号线，以及与每行的液晶元件对应地排列的多个公共连接线; 扫描线驱动电路; 信号线驱动电路; 以及公共连接线驱动电路，其将一个或多个公共连接线（第一公共连接线）和多个公共连接线（第二公共连接线）彼此电分离，并且电连接所述多个第二 公共连接线彼此独立地驱动第一公共连接线和第二连接线彼此。

公开(公告)号：US20090251629A1

公开(公告)日：2009-10-08

申请号：US12418319

申请日：2009-04-03

申请人： Daisuke Ito ,  Yoshitoshi Kida ,  Takeya Takeuchi ,  David Pusey ,  Peter Shadwell

发明人： Daisuke Ito ,  Yoshitoshi Kida ,  Takeya Takeuchi ,  David Pusey ,  Peter Shadwell

IPC分类号： G02F1/1343 ,  G02F1/136

CPC分类号： G09G3/3655 ,  G02F2001/134318 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2320/0209 ,  G09G2330/021

摘要： A liquid crystal display module including a liquid crystal display having a plurality of liquid crystal cells, a plurality of switches and a common connection, each liquid crystal cell being connected between a respective switch and a common connection. The common connection includes strips, each extending in a first direction and the strips being arranged side-by-side in a second direction. The liquid crystal cells are arranged in rows, each row being along and connected to a strip. The liquid crystal display has gate lines, each gate line operating a respective plurality of the switches. For dot inversion, each gate operates switches connected to respective liquid crystal cells of two adjacent rows. For each row, a first set of alternate liquid crystal cells are connected to respective switches operated by a respective gate line and a second set of interspersed liquid crystal cells are connected to respective switches operated by another respective gate line.

摘要翻译： 一种液晶显示模块，包括具有多个液晶单元的液晶显示器，多个开关和公共连接，每个液晶单元连接在相应的开关和公共连接之间。 公共连接包括每个沿第一方向延伸的条，并且条沿第二方向并排布置。 液晶单元排列成行，每排沿着条带连接。 液晶显示器具有栅极线，每个栅极线操作相应的多个开关。 对于点反转，每个栅极操作连接到两个相邻行的相应液晶单元的开关。 对于每行，第一组备用液晶单元连接到由相应的栅极线操作的各个开关，并且第二组散布的液晶单元连接到由另一个相应的栅极线操作的各个开关。

公开(公告)号：US20090128527A1

公开(公告)日：2009-05-21

申请号：US12230438

申请日：2008-08-28

申请人： Naoyuki Itakura ,  Yoshihiko Toyoshima ,  Tomoyuki Fukano ,  Satoshi Ono ,  Daisuke Ito ,  Yusuke Takahashi ,  Takeya Takeuchi ,  Yoshitoshi Kida

发明人： Naoyuki Itakura ,  Yoshihiko Toyoshima ,  Tomoyuki Fukano ,  Satoshi Ono ,  Daisuke Ito ,  Yusuke Takahashi ,  Takeya Takeuchi ,  Yoshitoshi Kida

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3655 ,  G09G2300/0426 ,  G09G2320/0204 ,  G09G2320/0219 ,  G09G2320/0223 ,  G09G2320/0247 ,  G09G2320/029

摘要： Disclosed herein is a display apparatus including: an available pixel section having a plurality of available pixel circuits; a plurality of scan lines; a plurality of capacitor lines; a plurality of signal lines; a driving circuit; and a monitor circuit wherein each of the available pixel circuits laid out on the available pixel section includes a display element having first and second pixel electrodes and a storage capacitor having first and second electrodes, in each of the available pixel circuits, the first pixel electrode and the first electrode are connected to one terminal of a switching device, in each of the available pixel circuits provided on any individual one of the rows, the second electrode is connected to the capacitor line provided for the individual row, and the common voltage signal with the level changing at time intervals determined in advance is supplied to the second pixel electrode of each of the display elements.

摘要翻译： 这里公开了一种显示装置，包括：具有多个可用像素电路的可用像素部分; 多条扫描线; 多个电容线; 多条信号线; 驱动电路; 以及监视器电路，其中布置在可用像素部分上的每个可用像素电路包括具有第一和第二像素电极的显示元件和具有第一和第二电极的存储电容器，在每个可用像素电路中，第一像素电极 并且第一电极连接到开关装置的一个端子，在设置在行中的任何一个的每个可用像素电路中，第二电极连接到为各行设置的电容器线，并且公共电压信号 其中预先确定的时间间隔的电平改变被提供给每个显示元件的第二像素电极。

公开(公告)号：US20090058488A1

公开(公告)日：2009-03-05

申请号：US12222860

申请日：2008-08-18

申请人： Werapong Jarupoonphol ,  Yoshitoshi Kida

发明人： Werapong Jarupoonphol ,  Yoshitoshi Kida

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K5/04 ,  H03K5/135 ,  H03K19/00361 ,  H03K19/00384

摘要： Disclosed herein is a delay circuit for performing one of a charge and a discharge in two stages, and delaying a signal, the delay circuit including an output section configured to output a delayed signal; two power supplies; and a delay inverter; wherein the delay inverter has a first transistor and a second transistor of an identical channel type for one of a first charge and a first discharge, the first transistor and the second transistor being connected in series with each other between the output section and one power supply, and the delay inverter has a third transistor of a different channel type from the first transistor and the second transistor for one of a second charge and a second discharge, the third transistor being connected in parallel with one of the first transistor and the second transistor.

摘要翻译： 这里公开了一种延迟电路，用于两级执行充电和放电中的一种，并延迟信号，该延迟电路包括被配置为输出延迟信号的输出部分; 两个电源; 和延时逆变器; 其中所述延迟反相器具有用于第一电荷和第一放电之一的相同沟道类型的第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管在所述输出部分和一个电源之间彼此串联连接 延迟反相器具有与第一晶体管不同的沟道类型的第三晶体管和用于第二电荷和第二放电之一的第二晶体管，第三晶体管与第一晶体管和第二晶体管中的一个并联连接 。

公开(公告)号：US07368945B2

公开(公告)日：2008-05-06

申请号：US11441879

申请日：2006-05-26

申请人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

发明人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

IPC分类号： H03K19/173 ,  H03K3/037

CPC分类号： G09G3/20 ,  G09G3/3648 ,  G09G5/18 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2310/08

摘要： When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs (12, 13), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit 15 with respect to the two TFFs (12, 13), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.

摘要翻译： 当通过使用具有大的元件特性变化的晶体管形成缓冲器时，可能会发生输入时钟脉冲与复位脉冲之间的定时偏差。 当定时的偏差变大时，会发生故障，相对于元件特性的变化，操作余量变小。 在形成在绝缘基板上并具有两个TFF（12,13）的定时产生电路中，用于产生点时钟DCK和频率与输入外部的主时钟MCK同步的频率不同的水平时钟HCK 在相对于两个TFF（12,13）的脉冲发生电路15处产生分离的复位脉冲drst和hrst，并且在单独的定时执行复位操作。 因此，即使当通过使用具有大的元件特性变化的TFT和粗略的处理规则形成每个电路时，也可以确保大的操作余量。

公开(公告)号：US07224200B2

公开(公告)日：2007-05-29

申请号：US10484953

申请日：2003-05-26

申请人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Hiroaki Ichikawa

发明人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Hiroaki Ichikawa

IPC分类号： H03L5/00

CPC分类号： G09G3/3688 ,  G09G3/3655 ,  G09G2300/0408 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0294 ,  H03K3/356165

摘要： In the structure in which an input signal IN and a reverse-phase signal XIN thereof are externally input, an external IC is required for generating the reverse-phase signal XIN, and the number of required input signal terminals is two.A level shift circuit formed on an insulating substrate, such as a glass substrate, using transistors with large characteristic variations, for example, TFTs with high thresholds Vth, includes a complementary generator unit (11) driven by a first power supply (VCC) having an amplitude voltage equal to the amplitude voltage of a signal externally input from the substrate to generate complementary signals from a single-phase input signal IN. The complementary signals generated by the complementary generator unit (11) are level-shifted by a level shift unit (14). Therefore, it is no longer necessary to externally input the reverse-phase signal XIN.

公开(公告)号：US20070109288A1

公开(公告)日：2007-05-17

申请号：US10563298

申请日：2004-07-06

申请人： Yoshitoshi Kida

发明人： Yoshitoshi Kida

IPC分类号： G09G5/00

CPC分类号： G09G3/3696 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0876 ,  G09G2310/027 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2330/022

摘要： The present invention is applied, for example, to a liquid crystal display apparatus in which drive circuitry is formed integrally on an insulating substrate, wherein processing results from circuit blocks 41A, 41B on the side of a higher power supply voltage are inputted into the side of a lower power supply voltage through active elements performing on-off operation complementarily, and by the fall of the power supply voltage on this higher side, the output of these active elements is set to a predetermined level.

摘要翻译： 本发明例如应用于其中驱动电路整体地形成在绝缘基板上的液晶显示装置，其中来自较高电源电压侧的电路块41A，41B的处理结果被输入到 通过有源元件互补地进行开 - 关操作的较低电源电压的一侧，并且由于该较高侧的电源电压的下降，这些有源元件的输出被设定为预定电平。

公开(公告)号：US20070109282A1

公开(公告)日：2007-05-17

申请号：US10561870

申请日：2004-07-06

申请人： Yoshitoshi Kida ,  Yoshiharu Nakajima

发明人： Yoshitoshi Kida ,  Yoshiharu Nakajima

IPC分类号： G09G5/00

CPC分类号： H03K3/356156 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2330/02 ,  G09G2330/021 ,  G11C19/00 ,  H03K3/0375

摘要： The present invention is a data transfer circuit applicable to a liquid crystal display apparatus with a drive circuit formed integral, for example, on an insulation substrate, configured such that only an inverted output of a latch result of a first latch section (41) or only a non-inverted output thereof is data-transferred to a second latch section (42), and that at least during a period of data transfer to the second latch section (42), a power supply voltage of the first latch section (41) is raised.

摘要翻译： 本发明是可应用于液晶显示装置的数据传输电路，该液晶显示装置具有例如在绝缘基板上形成为一体的驱动电路，该驱动电路被配置为仅使第一锁存部分（41）的锁存结果的反相输出或 仅将其非反相输出数据传送到第二锁存部分（42），并且至少在数据传送到第二锁存部分（42）期间，第一锁存部分（41）的电源电压 ）被提升。

公开(公告)号：US20060214694A1

公开(公告)日：2006-09-28

申请号：US11441879

申请日：2006-05-26

申请人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

发明人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

IPC分类号： H03K19/00

CPC分类号： G09G3/20 ,  G09G3/3648 ,  G09G5/18 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2310/08

摘要： When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs (12, 13), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit 15 with respect to the two TFFs (12, 13), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.