公开(公告)号：US20100226192A1

公开(公告)日：2010-09-09

申请号：US12659328

申请日：2010-03-04

申请人： Jong-Ho Moon ,  Seong-Jin Jang

发明人： Jong-Ho Moon ,  Seong-Jin Jang

IPC分类号： G11C7/00

CPC分类号： G11C7/1048 ,  G11C11/4096

摘要： A data path circuit of a semiconductor memory device includes: a bit line sense amplifier driven by a first power supply voltage; a local input/output line sense amplifier; a column selecting unit operatively connecting a pair of bit lines connected to the bit line sense amplifier and a pair of local input/output lines connected to the local input/output line sense amplifier in response to a column selection signal; and a local input/output line precharge unit precharging the pair of local input/output lines with a second power supply voltage different from the first power supply voltage during a period for which the column selection signal is in an inactive state.

摘要翻译： 半导体存储器件的数据路径电路包括：由第一电源电压驱动的位线读出放大器; 本地输入/输出线路读出放大器; 列选择单元，可操作地连接连接到位线读出放大器的一对位线和响应于列选择信号连接到本地输入/输出线读出放大器的一对本地输入/输出线; 以及本地输入/输出线预充电单元，在列选择信号处于非活动状态的期间，用与第一电源电压不同的第二电源电压对一对本地输入/输出线进行预充电。

公开(公告)号：US20100091601A1

公开(公告)日：2010-04-15

申请号：US12635751

申请日：2009-12-11

申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

摘要： A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.

摘要翻译： 一种用于消除半导体存储器件和存储器控制器之间的接口中的数据与时钟信号之间的偏斜的电路，包括存储从半导体存储器件输出的边沿信息的边缘信息存储单元，伪数据模式生成单元，其输出伪 数据，包括与实际发送的数据类似的模式;相位检测单元，其从边缘信息存储单元接收边缘信息，并从伪数据模式产生单元接收伪数据，以检测数据和时钟信号之间的相位差，并产生 相应的检测结果，以及相位控制单元，其根据来自相位检测单元的相应检测结果控制时钟信号的相位，以便消除数据写入和读取操作中的每数据输入/输出引脚偏移 的半导体存储器件。

公开(公告)号：US07499341B2

公开(公告)日：2009-03-03

申请号：US11601027

申请日：2006-11-17

申请人： Woo-Jin Lee ,  Hyun-Dong Kim ,  Seong-Jin Jang

发明人： Woo-Jin Lee ,  Hyun-Dong Kim ,  Seong-Jin Jang

IPC分类号： G11C7/10

CPC分类号： G11C29/48 ,  G11C7/1051 ,  G11C7/1069 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/14

摘要： A semiconductor memory device and a method of expanding a valid output data window are described. The semiconductor memory device includes a memory cell array and an output circuit. The memory cell array generates read data having a plurality of bits. The output circuit outputs the read data sequentially in response to a clock signal in a normal mode. On the other hand, the output circuit selectively outputs the bits of the read data by latching bits to be tested among bits of the read data, and by electrically disconnecting bits not to be tested among bits of the read data in response to a plurality of switch control signals in a test mode. Therefore a valid data window of an output data may be expanded.

摘要翻译： 描述半导体存储器件和扩展有效输出数据窗口的方法。 半导体存储器件包括存储单元阵列和输出电路。 存储单元阵列产生具有多个位的读取数据。 输出电路响应于正常模式下的时钟信号顺序地输出读取的数据。 另一方面，输出电路通过在读取数据的比特之间锁存待测试的比特来选择性地输出读取的数据的比特，并且响应于多个读取数据，通过电连接在读取的数据的比特之间的不被测试的比特 在测试模式下切换控制信号。 因此，可以扩展输出数据的有效数据窗口。

公开(公告)号：US07420387B2

公开(公告)日：2008-09-02

申请号：US11402123

申请日：2006-04-11

申请人： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

发明人： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

IPC分类号： H03K17/16

CPC分类号： H03K19/0005

摘要： Provided is a semiconductor device capable of controlling an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit and a control method used by the semiconductor device. The semiconductor device includes a control code generation unit generating a control code in response to a control signal, an addition unit adding an adjustment code to the control code to produce an adjusted control code, and an ODT circuit, wherein an impedance of the ODT circuit is adjusted in response to the adjusted control code. The semiconductor device can adjust the control code more precisely by adding or subtracting the adjustment code to or from the control code. Accordingly, the impedance of an OCD circuit or ODT circuit can be adjusted more precisely.

摘要翻译： 提供了能够控制芯片上终端（ODT）电路和芯片外驱动器（OCD）电路的半导体器件以及由半导体器件使用的控制方法。 半导体器件包括响应于控制信号产生控制代码的控制代码生成单元，向控制代码添加调整代码以产生调整后的控制代码的加法单元和ODT电路，其中ODT电路的阻抗 根据调整后的控制代码进行调整。 半导体器件可以通过向或从控制代码添加或减去调整代码来更精确地调整控制代码。 因此，可以更精确地调整OCD电路或ODT电路的阻抗。

公开(公告)号：US07376041B2

公开(公告)日：2008-05-20

申请号：US11024272

申请日：2004-12-27

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G11C7/00 ,  G11C7/10

CPC分类号： G11C7/22 ,  G11C7/1066

摘要： A semiconductor memory device includes a memory cell array to store data; a data input portion to output data to the memory cell array in response to a write control signal; a data output portion to output data from the memory cell array in response to a read control signal; a data I/O gate to transmit data outputted from the data input portion to the memory cell array in response to the write control signal, and transmitting data outputted from the memory cell array to the data output portion in response to the read control signal; and a data I/O controller to generate the read control signal and the write control signal having a smaller minimum cycle time than a minimum cycle time of the read control signal. The semiconductor memory device has an improved operation performance compared to one having a low operation frequency within an operable frequency range.

摘要翻译： 半导体存储器件包括用于存储数据的存储单元阵列; 数据输入部分，用于响应写控制信号将数据输出到存储单元阵列; 数据输出部分，用于响应于读取控制信号从存储单元阵列输出数据; 数据I / O门，用于响应于写控制信号将从数据输入部分输出的数据发送到存储单元阵列;以及响应于读控制信号将从存储单元阵列输出的数据发送到数据输出部分; 以及数据I / O控制器，用于产生具有比所读取的控制信号的最小周期时间更小的最小周期时间的读取控制信号和写入控制信号。 与在可操作频率范围内具有低工作频率的半导体存储器件相比，具有改进的操作性能。

公开(公告)号：US07366822B2

公开(公告)日：2008-04-29

申请号：US10840268

申请日：2004-05-07

申请人： Jin-Seok Kwak ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Sang-Bo Lee ,  Min-Sang Park ,  Chul-Soo Kim

发明人： Jin-Seok Kwak ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Sang-Bo Lee ,  Min-Sang Park ,  Chul-Soo Kim

IPC分类号： G06F12/00 ,  G11C8/00

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C11/4082 ,  G11C11/4087

摘要： A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.

摘要翻译： 半导体存储器件包括多个存储体。 数据路径可以被划分为读取数据路径和写入数据路径，因此并行处理写入和读取命令是可能的。 半导体存储器件可以包括地址库缓冲器，地址缓冲器，列预解码器和/或解码器。 半导体存储器件可以在一个时钟周期内开始执行存储体中的写入命令，并且在随后的时钟周期开始执行读取命令，因此总线效率增加和/或写入读取时间减少 。

公开(公告)号：US07187615B2

公开(公告)日：2007-03-06

申请号：US10943514

申请日：2004-09-17

申请人： Min-Sang Park ,  Yu-Lim Lee ,  Seong-Jin Jang

发明人： Min-Sang Park ,  Yu-Lim Lee ,  Seong-Jin Jang

IPC分类号： G11C8/00

CPC分类号： G11C8/12

摘要： A method for activating a word line segment of a semiconductor memory selected based on a row address provided to the memory can include activating a first word line segment selected by a row address and a command type and avoiding activating a second word line segment selected by the row address. Related devices are also disclosed.

摘要翻译： 用于激活基于提供给存储器的行地址选择的半导体存储器的字线段的方法可以包括激活由行地址和命令类型选择的第一字线段，并且避免激活由第二字线段选择的第二字线段 行地址。 还公开了相关设备。

公开(公告)号：US20060226868A1

公开(公告)日：2006-10-12

申请号：US11402123

申请日：2006-04-11

申请人： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

发明人： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

IPC分类号： H03K19/003

CPC分类号： H03K19/0005

摘要： Provided is a semiconductor device capable of controlling an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit and a control method used by the semiconductor device. The semiconductor device includes a control code generation unit generating a control code in response to a control signal, an addition unit adding an adjustment code to the control code to produce an adjusted control code, and an ODT circuit, wherein an impedance of the ODT circuit is adjusted in response to the adjusted control code. The semiconductor device can adjust the control code more precisely by adding or subtracting the adjustment code to or from the control code. Accordingly, the impedance of an OCD circuit or ODT circuit can be adjusted more precisely.

摘要翻译： 提供了能够控制芯片上终端（ODT）电路和芯片外驱动器（OCD）电路的半导体器件以及由半导体器件使用的控制方法。 半导体器件包括响应于控制信号产生控制代码的控制代码生成单元，向控制代码添加调整代码以产生调整后的控制代码的加法单元和ODT电路，其中ODT电路的阻抗 根据调整后的控制代码进行调整。 半导体器件可以通过向或从控制代码添加或减去调整代码来更精确地调整控制代码。 因此，可以更精确地调整OCD电路或ODT电路的阻抗。

公开(公告)号：US20050174858A1

公开(公告)日：2005-08-11

申请号：US11024272

申请日：2004-12-27

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G11C11/407 ,  G11C5/00 ,  G11C7/22 ,  G11C11/40 ,  G11C11/409

CPC分类号： G11C7/22 ,  G11C7/1066

摘要： A semiconductor memory device includes a memory cell array to store data; a data input portion to output data to the memory cell array in response to a write control signal; a data output portion to output data from the memory cell array in response to a read control signal; a data I/O gate to transmit data outputted from the data input portion to the memory cell array in response to the write control signal, and transmitting data outputted from the memory cell array to the data output portion in response to the read control signal; and a data I/O controller to generate the read control signal and the write control signal having a smaller minimum cycle time than a minimum cycle time of the read control signal. The semiconductor memory device has an improved operation performance compared to one having a low operation frequency within an operable frequency range.

摘要翻译： 半导体存储器件包括用于存储数据的存储单元阵列; 数据输入部分，用于响应写控制信号将数据输出到存储单元阵列; 数据输出部分，用于响应于读取控制信号从存储单元阵列输出数据; 数据I / O门，用于响应于写控制信号将从数据输入部分输出的数据发送到存储单元阵列;以及响应于读控制信号将从存储单元阵列输出的数据发送到数据输出部分; 以及数据I / O控制器，用于产生具有比所读取的控制信号的最小周期时间更小的最小周期时间的读取控制信号和写入控制信号。 与在可操作频率范围内具有低工作频率的半导体存储器件相比，具有改进的操作性能。

公开(公告)号：US06850110B2

公开(公告)日：2005-02-01

申请号：US10108276

申请日：2002-03-27

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G11C5/14 ,  H02M3/07 ,  G06F7/64

CPC分类号： H02M3/073 ,  H02M2003/075

摘要： A voltage generating circuit and method thereof for preventing a current from flowing from a voltage generating node to a pumping node in transiting of the circuit from an active operation to a pre-charge operation are provided. The voltage generating circuit comprises a pre-charge circuit for pre-charging a pumping node and a voltage transmitting control node during a pre-charge operation; a voltage pumping circuit for pumping a signal at the pumping node during an active operation; a voltage transmitting circuit for transmitting the signal from the pumping node to a voltage generating node in response to a signal at the voltage transmitting control node during the active operation; and a countercurrent preventing circuit for varying the signal at the voltage transmitting control node based on the signal at the pumping node during the pre-charge operation and for preventing a current from flowing between the pumping node and the voltage transmitting control node during the active operation.

摘要翻译： 提供一种电压产生电路及其方法，用于防止电流从电压产生节点流向泵送节点，以将电路从有源操作转移到预充电操作。 电压产生电路包括用于在预充电操作期间预充电泵浦节点和电压发送控制节点的预充电电路; 用于在主动操作期间泵送泵送节点处的信号的电压泵浦电路; 电压发送电路，用于在主动操作期间响应于电压发送控制节点处的信号将信号从泵送节点发送到电压产生节点; 以及逆流防止电路，用于在预充电操作期间基于泵送节点处的信号来改变电压发送控制节点处的信号，并且用于在主动操作期间防止在泵送节点和电压发送控制节点之间流动的电流 。