公开(公告)号：US09319353B2

公开(公告)日：2016-04-19

申请号：US12491219

申请日：2009-06-24

申请人： Li-Han Liang ,  Tao-Chun Wang ,  Kuo-Nan Yang ,  Shieh-Hsing Kuo

发明人： Li-Han Liang ,  Tao-Chun Wang ,  Kuo-Nan Yang ,  Shieh-Hsing Kuo

IPC分类号： H04L29/06 ,  H04K1/00 ,  H04L12/861 ,  G06F21/62

CPC分类号： H04L49/90 ,  G06F21/6218 ,  G06F2221/2107 ,  H04L49/9057 ,  H04L63/0428 ,  H04L63/0442 ,  H04L63/0485

摘要： A network task offload apparatus includes an offload circuit and a buffer scheduler. The offload circuit performs corresponding network task processing on a plurality of packets in parallel according to an offload command. The buffer scheduler includes a buffer control unit and a plurality of buffer units. The plurality of buffer units are controlled by the buffer control unit and are scheduled to store the processed packets.

摘要翻译： 网络任务卸载装置包括卸载电路和缓冲器调度器。 卸载电路根据卸载命令并行地对多个分组进行相应的网络任务处理。 缓冲器调度器包括缓冲器控制单元和多个缓冲单元。 多个缓冲单元由缓冲器控制单元控制，并被调度以存储经处理的分组。

公开(公告)号：US07823045B2

公开(公告)日：2010-10-26

申请号：US11463900

申请日：2006-08-11

申请人： Chien-Chih Chen ,  Hui-Huang Chang ,  Shieh-Hsing Kuo ,  Hsin-Hung Lu

发明人： Chien-Chih Chen ,  Hui-Huang Chang ,  Shieh-Hsing Kuo ,  Hsin-Hung Lu

IPC分类号： G11C29/00

CPC分类号： G11B20/18 ,  G11B20/182 ,  G11B20/1833 ,  G11B2020/1062 ,  G11B2020/10787 ,  G11B2020/10796 ,  G11B2020/1826 ,  G11B2220/2562 ,  G11C2029/0409

摘要： An error correction device includes a decoding unit, an error buffer, an error classifying unit and an error correction unit. The decoding unit reads data from a main memory and performs error detection on the data to generate error values and error addresses. Then, the error buffer temporarily stores the error values and the error addresses. The error classifying unit classifies the error addresses stored in the error buffer into a plurality of subclasses, where error values and error addresses which correspond to the same row of the main memory are classified into the same subclass. Finally, the error correction unit performs an error correction on the data stored in the main memory according to the plurality of subclasses. The error correction device therefore can reduce the amount of the change-row operations of the main memory so that the memory efficiency is increased.

摘要翻译： 误差校正装置包括解码单元，误差缓冲器，误差分类单元和纠错单元。 解码单元从主存储器读取数据，对数据进行错误检测，生成错误值和错误地址。 然后，错误缓冲区临时存储错误值和错误地址。 错误分类单元将存储在错误缓冲器中的错误地址分类为多个子类，其中对应于主存储器的同一行的错误值和错误地址被分类为相同的子类。 最后，误差校正单元根据多个子类对存储在主存储器中的数据进行纠错。 因此，误差校正装置可以减少主存储器的改变行操作的量，从而提高存储器效率。

公开(公告)号：US20080184091A1

公开(公告)日：2008-07-31

申请号：US12023048

申请日：2008-01-31

申请人： Chien-Chih Chen ,  Shieh-Hsing Kuo

发明人： Chien-Chih Chen ,  Shieh-Hsing Kuo

IPC分类号： H03M13/00

CPC分类号： G11B20/1833 ,  G11B2220/2537 ,  H03M13/09

摘要： An EDC generating circuit includes a memory unit, an EDC generating circuit, a header generator and an EDC correcting circuit. The EDC generating circuit, which is coupled to the memory unit, is used for generating a first EDC according to at least one main data, and for storing the first EDC to the memory unit. The header generator, which is coupled to the memory unit, is used for generating a header according to header information. The EDC correcting circuit, which is coupled to the memory unit, is used for reading the first EDC from the memory unit and for correcting the first EDC according to the header to generate a second EDC.

摘要翻译： EDC生成电路包括存储单元，EDC生成电路，头部生成器以及EDC校正电路。 耦合到存储器单元的EDC生成电路用于根据至少一个主数据产生第一EDC，并用于将第一EDC存储到存储器单元。 耦合到存储器单元的标题生成器用于根据报头信息生成报头。 耦合到存储器单元的EDC校正电路用于从存储器单元读取第一EDC并根据标题校正第一EDC以产生第二EDC。

公开(公告)号：US07272177B2

公开(公告)日：2007-09-18

申请号：US10687671

申请日：2003-10-20

申请人： Hou-Wei Lin ,  Shieh-Hsing Kuo ,  Meng-Han Hsieh ,  Kuang-Yu Yen

发明人： Hou-Wei Lin ,  Shieh-Hsing Kuo ,  Meng-Han Hsieh ,  Kuang-Yu Yen

IPC分类号： H03H7/30

CPC分类号： H04L25/03038 ,  H03H21/0012 ,  H04L7/0062 ,  H04L25/03235 ,  H04L2025/03363 ,  H04L2025/03477

摘要： A transceiver of a communication system is disclosed. The transceiver comprises a front-end receiver for receiving a receiving signal and converting to a first signal with a pre-cursor component and a post-cursor component, a noise canceller coupled to the front-end receiver 10 for generating a second signal through eliminating the noise of the first signal, a Feed-Forward Equalizer (FFE) coupled to the noise canceller for generating a third signal through eliminating the pre-cursor component in the second signal according to a transfer function including a plurality of adjustable constants, wherein the adjustable constants includes a main-tap and the value of the main-tap is predetermined, and a decoding system coupled to the FFE for decoding the third signal and eliminating the post-cursor component in the third signal.

摘要翻译： 公开了一种通信系统的收发器。 收发器包括前端接收器，用于接收接收信号并用前置光标分量和后光标分量转换成第一信号;噪声消除器，耦合到前端接收机10，用于通过消除产生第二信号 第一信号的噪声，耦合到噪声消除器的前馈均衡器（FFE），用于通过根据包括多个可调常数的传递函数消除第二信号中的前置分量来产生第三信号，其中， 可调常数包括主抽头，并且主抽头的值是预定的，以及耦合到FFE的解码系统，用于解码第三信号并消除第三信号中的后标光分量。

公开(公告)号：US20060008255A1

公开(公告)日：2006-01-12

申请号：US10710371

申请日：2004-07-06

申请人： Kuang-Yu Yen ,  Shieh-Hsing Kuo

发明人： Kuang-Yu Yen ,  Shieh-Hsing Kuo

IPC分类号： H04N5/781

CPC分类号： G11B20/18 ,  G11B20/10009 ,  H04N5/85

摘要： A device for decoding a disc read signal generated by accessing data stored in a disc storage medium. The device includes: a multi-level analog-to-digital converter (ADC) for digitizing the disc read signal to generate a digitized disc read signal; a confidence index generating circuit for generating a plurality of confidence indexes according to the magnitude of the digitalized disc read signal; a demodulator coupled to the multi-level ADC for demodulating the digitalized disc read signal to generate a demodulated disc read signal; and an Error Correction Code (ECC) decoder coupled to the demodulator for decoding the demodulated disc read signal according to the confidence indexes.

摘要翻译： 一种用于解码通过访问存储在盘存储介质中的数据而生成的盘读信号的装置。 该装置包括：用于数字化盘读取信号以产生数字化盘读信号的多电平模数转换器（ADC）; 置信指标产生电路，用于根据数字化盘读信号的大小产生多个置信指标; 耦合到多电平ADC的解调器，用于解调数字化盘读取信号以产生解调的盘读信号; 以及耦合到解调器的纠错码（ECC）解码器，用于根据置信指数对解调的盘读信号进行解码。

公开(公告)号：US08166378B2

公开(公告)日：2012-04-24

申请号：US13214249

申请日：2011-08-22

申请人： Chien-Chih Chen ,  Shieh-Hsing Kuo

发明人： Chien-Chih Chen ,  Shieh-Hsing Kuo

IPC分类号： H03M13/00

CPC分类号： G11B20/1833 ,  G11B2220/2537 ,  H03M13/09

摘要： An encoding circuit is disclosed, which has a memory unit, an EDC generating circuit, a scrambler, a header generator, an EDC correcting circuit, and an encoder. The EDC generating circuit generates a first EDC according to at least one main data. The scrambler generates a scrambled main data according to the main data. The header generator generates a header according to header information. The EDC correcting circuit, corrects the first EDC according to the header to generate a second EDC. The encoder encodes an optical data according to the second EDC and the scrambled main data.

摘要翻译： 公开了一种编码电路，其具有存储单元，EDC生成电路，加扰器，报头发生器，EDC校正电路和编码器。 EDC生成电路根据至少一个主数据生成第一EDC。 扰频器根据主数据产生加扰的主数据。 标题生成器根据标题信息生成报头。 EDC校正电路根据报头校正第一EDC以产生第二EDC。 编码器根据第二EDC和加扰的主数据对光数据进行编码。

公开(公告)号：US20100165865A1

公开(公告)日：2010-07-01

申请号：US12648993

申请日：2009-12-29

申请人： Lie-Way Fang ,  Shieh-Hsing Kuo ,  Chia-Ying Chiu ,  Mei-chao Yeh

发明人： Lie-Way Fang ,  Shieh-Hsing Kuo ,  Chia-Ying Chiu ,  Mei-chao Yeh

IPC分类号： H04L12/26 ,  H04L12/66 ,  H04L12/56

CPC分类号： H04L12/10

摘要： Network interface apparatus with power management is disclosed, which comprises a physical layer circuit, for receiving a packet on a network; a media access control circuit, for performing the media access processing on the packet to output a processed packet; an interface circuit, coupled to the media access control layer, for transmitting the processed packet to a bus; a detecting circuit, coupled to the physical layer circuit, for detecting a transmitting status of the packet on the network to output a detecting signal; a loading control circuit, coupled to the detecting circuit, for control a load positioned in the interface circuit according to the detecting signal.

摘要翻译： 公开了具有电源管理的网络接口装置，其包括用于在网络上接收分组的物理层电路; 媒体接入控制电路，用于对所述分组执行媒体接入处理以输出处理的分组; 接口电路，耦合到媒体接入控制层，用于将经处理的分组传送到总线; 耦合到所述物理层电路的检测电路，用于检测所述网络上的分组的发送状态以输出检测信号; 耦合到检测电路的负载控制电路，用于根据检测信号控制位于接口电路中的负载。

公开(公告)号：US20090193109A1

公开(公告)日：2009-07-30

申请号：US12354786

申请日：2009-01-16

申请人： Shieh-Hsing Kuo ,  Ta-Chin Tseng ,  Ming-Je Li ,  Ting-Fa Yu

发明人： Shieh-Hsing Kuo ,  Ta-Chin Tseng ,  Ming-Je Li ,  Ting-Fa Yu

IPC分类号： G06F15/16 ,  G06F1/32

CPC分类号： G06F1/3209 ,  H04L69/323

摘要： A power-saving network apparatus includes a MAC and a PHY. The PHY includes a transmitter and a receiver. The transmitter executes the operations of: transmitting a data signal to a remote network apparatus according to output packets of the MAC when the transmitter enters a normal state; transmitting an idle signal to the remote network apparatus when the transmitter enters an idle state; transmitting an indication signal to the remote network apparatus to notify it to enter a low power state, wherein the indication signal is different from the idle signal; entering the idle state or the normal state from the low power state in response to at least one of a predetermined period and a transmitting enable signal.

摘要翻译： 省电网络装置包括MAC和PHY。 PHY包括发射机和接收机。 发射机执行以下操作：当发射机进入正常状态时，根据MAC的输出分组向远程网络设备发送数据信号; 当发射机进入空闲状态时，向远程网络设备发送空闲信号; 向所述远程网络装置发送指示信号以通知其进入低功率状态，其中所述指示信号与所述空闲信号不同; 响应于预定周期和发送使能信号中的至少一个，从低功率状态进入空闲状态或正常状态。

公开(公告)号：US07460593B2

公开(公告)日：2008-12-02

申请号：US10709462

申请日：2004-05-07

申请人： Hou-Wei Lin ,  Shieh-Hsing Kuo ,  Yi-Lin Li ,  Kuang-Yu Yen

发明人： Hou-Wei Lin ,  Shieh-Hsing Kuo ,  Yi-Lin Li ,  Kuang-Yu Yen

IPC分类号： H04B1/38 ,  H04L5/16 ,  H04L27/10 ,  H04L27/18

CPC分类号： H04L25/03057 ,  H04L25/061 ,  H04L2025/0349

摘要： A signal processing device for processing a passband signal to generate an equalized signal includes a passband adaptive equalizer for generating the equalized signal according to the passband signal, including at least one feed-forward equalizer (FFE) and one feedback equalizer (FBE), and a multilevel quantizer coupled with the passband adaptive equalizer for selectively utilizing a single predetermined threshold or a plurality of multiple predetermined thresholds to quantize the equalized signal in order to generate a sliced signal.

摘要翻译： 用于处理通带信号以产生均衡信号的信号处理装置包括通带自适应均衡器，用于根据通带信号产生包括至少一个前馈均衡器（FFE）和一个反馈均衡器（FBE）的均衡信号，以及 与通带自适应均衡器耦合的多电平量化器，用于选择性地利用单个预定阈值或多个多个预定阈值来量化均衡信号以产生分片信号。

公开(公告)号：US20080250258A1

公开(公告)日：2008-10-09

申请号：US12060356

申请日：2008-04-01

申请人： Shieh-Hsing Kuo ,  Ming-Je Li ,  Shian-Ru Lin ,  Ting-Fa Yu

发明人： Shieh-Hsing Kuo ,  Ming-Je Li ,  Shian-Ru Lin ,  Ting-Fa Yu

IPC分类号： G06F1/32

CPC分类号： G06F1/3237 ,  G06F1/3209 ,  Y02D10/128

摘要： A network processor includes a transceiver circuit, a network data processing unit, and a clock signal control unit. The transceiver circuit transmits and receives a network signal, compares a voltage level of the network signal with a threshold value, outputs a comparison result, and operates under a first clock signal. The network data processing unit is coupled to the transceiver circuit to process the network signal, and operates under a second clock signal different from the first clock signal. The clock signal control unit disables supply of the second clock signal to the network data processing unit when the voltage level is smaller than the threshold value, and enables supply of the second clock signal to the network data processing unit when the voltage level is not smaller than the threshold value. An energy saving method for a network processor is also disclosed.

摘要翻译： 网络处理器包括收发器电路，网络数据处理单元和时钟信号控制单元。 收发电路发送和接收网络信号，将网络信号的电压电平与阈值进行比较，输出比较结果，并在第一时钟信号下工作。 网络数据处理单元耦合到收发器电路以处理网络信号，并在与第一时钟信号不同的第二时钟信号下工作。 当电压电平小于阈值时，时钟信号控制单元禁止向网络数据处理单元提供第二时钟信号，并且当电压电平不小于时能够向网络数据处理单元提供第二时钟信号 超过阈值。 还公开了一种用于网络处理器的节能方法。