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    PROGRAM VERIFY PAIRING IN A MULTI-LEVEL CELL MEMORY DEVICE
    77.
    发明公开
    PROGRAM VERIFY PAIRING IN A MULTI-LEVEL CELL MEMORY DEVICE 审中-公开

    公开(公告)号：US20230170033A1

    公开(公告)日：2023-06-01

    申请号：US17987780

    申请日：2022-11-15

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Luyen Vu ,  Lawrence Celso Miranda ,  Jeffrey Ming-Hung Tsai

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/3459 ,  G11C16/26 ,  G11C16/102

    Abstract: Control logic in a memory device initiates a first loop of a program operation, the first loop comprising (a) a program phase where a plurality of memory cells associated with a selected wordline in a block of the memory array are programmed to respective ones of a plurality of programming levels and (b) a corresponding program verify phase. The control logic further identifies memory cells of the plurality of memory cells associated with a first sub-set of the plurality of programming levels to be verified during the program verify phase, the first sub-set comprising two or more dynamically selected programming levels comprising at least a lowest programming level and a second lowest programing level of the respective ones of the plurality of programming levels. The control logic further causes a first program verify voltage to be applied to the selected wordline during the program verify phase, and performs concurrent sensing operations on the identified memory cells of the plurality of memory cells associated with the first sub-set of the plurality programming levels to determine whether the identified memory cells were programmed to respective program verify threshold voltages corresponding to the first sub-set of the plurality of programming levels during the program phase of the first loop of the program operation.

    Memory plane access management
    78.
    发明授权
    Memory plane access management 有权

    公开(公告)号：US11568933B1

    公开(公告)日：2023-01-31

    申请号：US17458840

    申请日：2021-08-27

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Robert W. Strong ,  William Akin ,  Jeremy Binfet

    IPC: G11C16/22 ,  G11C16/04 ,  G11C16/24 ,  G11C16/34 ,  G11C16/30

    Abstract: A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

    STATUS POLLING BASED ON DIE-GENERATED PULSED SIGNAL
    79.
    发明申请
    STATUS POLLING BASED ON DIE-GENERATED PULSED SIGNAL 有权

    公开(公告)号：US20230024167A1

    公开(公告)日：2023-01-26

    申请号：US17590650

    申请日：2022-02-01

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Dheeraj Srinivasan

    IPC: G06F3/06

    Abstract: A memory system includes multiple dice having multiple planes. A processing device is coupled to the dice and performs controller operations including receiving a status indicator signal comprising a pulse that is asserted by one or more planes of the multiple dice. In response to receiving the pulse, the processing device performs at least one of: a first status check of dice operations being performed by the multiple dice at an expiration of a polling delay period; or a second status check of the dice operations in response to detecting the pulse being deasserted. The processing device terminates performances of status checks while the status indicator signal remains deasserted.

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