公开(公告)号：US20160189763A1

公开(公告)日：2016-06-30

申请号：US15063140

申请日：2016-03-07

Applicant: Micron Technology, Inc.

Inventor： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

IPC: G11C11/4076

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1066 ,  G11C7/1072 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

Abstract: Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

Abstract translation: 公开了系统，装置和方法。 在一种这样的方法的实施例中，一种对接收到的命令信号进行解码的方法，该方法包括将接收的命令信号与在时钟信号的第一时钟沿提供给存储器地址节点的信号相结合地解码，以产生多个存储器 控制信号。 接收到的命令信号与在时钟信号的第一时钟沿提供给存储器地址节点的信号相结合表示存储器命令。 此外，在时钟信号的第二时钟沿提供给存储器地址节点的信号不与所接收的命令信号组合解码。 存储器命令可以是减少功率命令和/或无操作命令。

公开(公告)号：US20150350082A1

公开(公告)日：2015-12-03

申请号：US14724510

申请日：2015-05-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： J. Thomas Pawlowski

IPC: H04L12/801 ,  H04L12/873 ,  H04L12/825

CPC classification number: G06F3/0619 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0617 ,  G06F3/0644 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0683 ,  G06F3/0685 ,  G06F3/0688 ,  G06F11/07 ,  G06F11/0727 ,  G06F11/073 ,  G06F11/076 ,  G06F11/10 ,  G06F11/1016 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F13/16 ,  G06F13/38 ,  G11C29/52 ,  H04L1/189 ,  H04L47/12 ,  H04L47/25 ,  H04L47/52 ,  Y02D10/14

Abstract: A method may include transmitting, via a processor, a plurality of packets to a receiving component, such that the plurality of packets corresponds to a plurality of data operations configured to access a memory component. The plurality of packets is stored in a buffer of the receiving component upon receipt. The method may also include determining, via the processor, whether an available capacity of the buffer is less than a threshold decreasing a transmission rate of the plurality of packets when the available capacity is less than the threshold.

Abstract translation: 方法可以包括经由处理器将多个分组发送到接收组件，使得所述多个分组对应于被配置为访问存储器组件的多个数据操作。 多个分组在接收时被存储在接收组件的缓冲器中。 该方法还可以包括：当可用容量小于阈值时，经由处理器确定缓冲器的可用容量是否小于降低多个分组的传输速率的阈值。

公开(公告)号：US20140244948A1

公开(公告)日：2014-08-28

申请号：US14269873

申请日：2014-05-05

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Dan Skinner ,  J. Thomas Pawlowski

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0683 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12

Abstract: Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.

Abstract translation: 提供具有内部处理器的记忆和在这种存储器内的数据通信方法。 一个这样的存储器可以包括提取单元，其被配置为基于要访问的存储体的可用性来基本上控制对存储器阵列执行命令。 取出单元可以接收包括指示数据是从数据读取还是写入银行的指令的指令以及要从银行读取或写入银行的数据的地址。 提取单元可以基于银行的可用性来执行命令。 在一个实施例中，当激活的库可用时，控制逻辑与提取单元进行通信。 在另一实现中，提取单元可以基于当已经执行了激活的存储体中的先前命令时设置的定时器等待存储体可用。