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    PACKAGE-ON-PACKAGE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING THE SAME
    73.
    发明申请
    PACKAGE-ON-PACKAGE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220028771A1

    公开(公告)日：2022-01-27

    申请号：US17493352

    申请日：2021-10-04

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Jack E. Murray

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

    SEMICONDUCTOR DEVICES WITH FLEXIBLE REINFORCEMENT STRUCTURE
    74.
    发明申请
    SEMICONDUCTOR DEVICES WITH FLEXIBLE REINFORCEMENT STRUCTURE 有权

    公开(公告)号：US20210384043A1

    公开(公告)日：2021-12-09

    申请号：US16896043

    申请日：2020-06-08

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Chan H. Yoo

    IPC: H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/29

    Abstract: Methods for manufacturing semiconductor devices having a flexible reinforcement structure, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes electrically coupling at least one semiconductor die to a redistribution structure on a first carrier. The semiconductor die can include a first surface connected to the redistribution structure and a second surface spaced apart from the redistribution structure. The method also includes reducing a thickness of the semiconductor die to no more than 10 μm. The method further includes coupling a flexible reinforcement structure to the second surface of the at least one semiconductor die.

    Methods and systems for manufacturing pillar structures on semiconductor devices
    75.
    发明授权
    Methods and systems for manufacturing pillar structures on semiconductor devices 有权

    公开(公告)号：US11081460B2

    公开(公告)日：2021-08-03

    申请号：US16236237

    申请日：2018-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Suresh Yeruva ,  Owen R. Fay ,  Sameer S. Vadhavkar ,  Adriel Jebin Jacob Jebaraj ,  Wayne H. Huang

    IPC: H01L23/00

    Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.

    Semiconductor Device Assembly with Pillar Array
    76.
    发明申请
    Semiconductor Device Assembly with Pillar Array 有权

    公开(公告)号：US20210183662A1

    公开(公告)日：2021-06-17

    申请号：US17189006

    申请日：2021-03-01

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Akshay N. Singh ,  Kyle K. Kirby

    IPC: H01L21/48 ,  H01L21/66 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48

    Abstract: A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.

    Encapsulated solder TSV insertion interconnect
    77.
    发明授权
    Encapsulated solder TSV insertion interconnect 有权

    公开(公告)号：US11018056B1

    公开(公告)日：2021-05-25

    申请号：US16671577

    申请日：2019-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Kyle K. Kirby ,  Owen R. Fay

    IPC: H01L21/76 ,  H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L21/463 ,  H01L21/60

    Abstract: A method of coupling a first semiconductor device to a second semiconductor device can include encapsulating solder balls on a first surface of a first substrate of the first semiconductor device with an encapsulant material. In some embodiments, the method includes removing a portion of the encapsulant material and a portion the solder balls to form a mating surface. The method can include reflowing the solder balls. In some embodiments, the method includes inserting exposed conductive pillars of the second semiconductor device into the reflowed solder balls.

    HIGH DENSITY PILLAR INTERCONNECT CONVERSION WITH STACK TO SUBSTRATE CONNECTION
    78.
    发明申请
    HIGH DENSITY PILLAR INTERCONNECT CONVERSION WITH STACK TO SUBSTRATE CONNECTION 有权

    公开(公告)号：US20210134725A1

    公开(公告)日：2021-05-06

    申请号：US16671558

    申请日：2019-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

    Abstract: A semiconductor device assembly can include a semiconductor device having a substrate and vias electrically connected to circuitry of the semiconductor device. Individual vias can have an embedded portion extending from the first side to the second side of the substrate and an exposed portion projecting from the second side of the substrate. The assembly can include a density-conversion connector comprising a connector substrate and a first array of contacts formed at the first side thereof, the first array of contacts occupying a first footprint area on the first side thereof, and wherein individual contacts of the first array are electrically connected to the exposed portion of a corresponding via of the semiconductor device. The assembly can include a second array of contacts electrically connected to the first array, formed at the second side of the connector substrate, and occupying a second footprint area larger than the first footprint area.

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