公开(公告)号：US08476698B2

公开(公告)日：2013-07-02

申请号：US12709114

申请日：2010-02-19

申请人： Lingpeng Guan ,  Anup Bhalla ,  Tinggang Zhu ,  Madhur Bobde

发明人： Lingpeng Guan ,  Anup Bhalla ,  Tinggang Zhu ,  Madhur Bobde

IPC分类号： H01L29/72

CPC分类号： H01L29/7823 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/47 ,  H01L29/7811

摘要： A superjunction device and methods for layout design and fabrication of a superjunction device are disclosed. A layout of active cell column structures can be configured so that a charge due to first conductivity type dopants balances out charge due to second conductivity type dopants in a doped layer in an active cell region. A layout of end portions of the active cell column structures proximate termination column structures can be configured so that a charge due to the first conductivity type dopants in the end portions and a charge due to the first conductivity type dopants in the termination column structures balances out charge due to the second conductivity type dopants in a portion of the doped layer between the termination column structures and the end portions.

公开(公告)号：US20130029461A1

公开(公告)日：2013-01-31

申请号：US13192385

申请日：2011-07-27

申请人： ANUP BHALLA ,  Madhur Bobde ,  Yongping Ding ,  Xiaotian Zhang ,  Yueh-Se Ho

发明人： ANUP BHALLA ,  Madhur Bobde ,  Yongping Ding ,  Xiaotian Zhang ,  Yueh-Se Ho

IPC分类号： H01L21/331

CPC分类号： H01L29/7395 ,  H01L21/2636 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/66333

摘要： A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

摘要翻译： 用于制造阳极短路场效应绝缘栅双极晶体管（IGBT）的方法包括选择性地形成具有相反导电类型的第一和第二半导体注入区。 可以将第二导电类型的场阻挡层生长到衬底或植入衬底中。 外延层可以在衬底上或场停止层上生长。 在外延层内形成一个或多个绝缘栅双极晶体管（IGBT）元件单元。

公开(公告)号：US08288839B2

公开(公告)日：2012-10-16

申请号：US12433358

申请日：2009-04-30

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/866

CPC分类号： H01L29/861 ,  H01L27/0259 ,  H01L29/10 ,  H01L29/6609

摘要： A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.

摘要翻译： 垂直瞬态电压抑制（TVS）器件包括：第一导电类型的半导体衬底，其中衬底被重掺杂;第一导电类型的外延层，形成在衬底上，其中外延层具有第一厚度;以及基极区 形成在外延层中的第二导电类型，其中基极区位于外延层的中间区域中。 基极区域和外延层在基极区域的两侧提供基本对称的垂直掺杂分布。 在一个实施例中，通过高能量注入形成基极区域。 在另一个实施例中，基底区形成为掩埋层。 选择外延层和基极区域的掺杂浓度以将TVS器件配置为基于穿通二极管的TVS或雪崩模式TVS。

公开(公告)号：US20110049564A1

公开(公告)日：2011-03-03

申请号：US12584151

申请日：2009-08-31

申请人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

发明人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L21/336 ,  H01L21/331

CPC分类号： H01L29/66712 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66325 ,  H01L29/7395 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

摘要翻译： 本发明公开了一种在半导体衬底中制造半导体功率器件的方法，包括有源电池区域和端接区域。 该方法包括以下步骤：a）在终端区域以及半导体衬底的顶表面上的活性单元区域中生长和构图场氧化物层b）在半导体衬底的顶表面上沉积并构图多晶硅层 在距离场氧化物层的间隙距离处; c）执行空白体掺杂剂注入以在所述半导体衬底中形成与所述间隙区基本对准的体掺杂区，随后将所述体掺杂区扩散到所述半导体衬底中的体区; d）植入包含在并且具有比身体区域更高的掺杂剂浓度的高浓度体 - 掺杂剂区域，以及e）将源掩模施加到具有与身体区域相反的导电性的源区域，其中源区域包含在身体区域中， 被高浓度体 - 掺杂区域包围。

公开(公告)号：US09882049B2

公开(公告)日：2018-01-30

申请号：US14507311

申请日：2014-10-06

申请人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

发明人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/739 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/08

CPC分类号： H01L29/7828 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66666 ,  H01L29/7806

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

公开(公告)号：US09876073B2

公开(公告)日：2018-01-23

申请号：US15479281

申请日：2017-04-05

申请人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

发明人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  H01L29/872 ,  H01L29/10 ,  H01L29/739

CPC分类号： H01L29/0634 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

公开(公告)号：US09647059B2

公开(公告)日：2017-05-09

申请号：US14298922

申请日：2014-06-08

申请人： Lingping Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

发明人： Lingping Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

IPC分类号： H01L21/8238 ,  H01L29/06 ,  H01L21/225 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/266

CPC分类号： H01L29/0634 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802

摘要： This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types. Then the manufacturing processes proceed by carrying out a device manufacturing process on a top side of the epitaxial layer on top of the dopant regions of the alternating conductivity types with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

公开(公告)号：US20170069740A9

公开(公告)日：2017-03-09

申请号：US13892259

申请日：2013-05-11

申请人： Madhur Bobde ,  Anup Bhalla

发明人： Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/739 ,  H01L21/22 ,  H01L29/66

摘要： This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.

摘要翻译： 本发明公开了一种形成在半导体衬底中的绝缘栅双极晶体管（IGBT）器件。 IGBT器件具有分裂屏蔽沟槽栅极，其包括上栅极段和下屏蔽段。 IGBT器件还可以包括填充有离开分屏蔽沟槽栅极一定距离设置的电介质层的虚拟沟槽。 IGBT器件还包括在分屏蔽沟槽栅极和虚拟沟槽之间延伸的体区，其围绕半导体衬底的顶表面附近的分离屏蔽沟槽栅极的源极区域。 所述IGBT器件还包括设置在所述体区域的下方且位于所述半导体衬底的底表面的底体 - 掺杂剂集电极区域上方的源 - 掺杂剂漂移区上方的重掺杂N区域。 在替代实施例中，IGBT可以包括具有沟槽屏蔽电极的平面栅极。

公开(公告)号：US20160372542A9

公开(公告)日：2016-12-22

申请号：US14329936

申请日：2014-07-12

申请人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

发明人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC分类号： H01L29/06 ,  H01L21/761 ,  H01L29/78

CPC分类号： H01L29/0623 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

公开(公告)号：US20160013267A1

公开(公告)日：2016-01-14

申请号：US14329936

申请日：2014-07-12

申请人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

发明人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC分类号： H01L29/06 ,  H01L21/761 ,  H01L29/78

CPC分类号： H01L29/0623 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。 边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。 边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。