公开(公告)号：US08878292B2

公开(公告)日：2014-11-04

申请号：US12074280

申请日：2008-03-02

申请人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

发明人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/739

CPC分类号： H01L29/7828 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66666

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件。 半导体功率器件包括沟槽栅极，每个沟槽栅极具有在由侧壁间隔物围绕的半导体衬底的顶表面之上延伸的伸出栅极段。 半导体功率器件还包括与基本上平行于沟槽栅极的侧壁间隔开的开口的槽。 粘贴门区段还包括由侧壁间隔物围绕的绝缘材料构成的盖。 阻挡金属层覆盖盖的顶表面并且覆盖在侧壁间隔物上并在槽的顶表面上方延伸。 这些槽填充有与栅极段相同的栅极材料，用作附加栅电极，用于提供向沟槽栅极延伸的耗尽层，借此栅极与沟槽栅极之间的漂移区域完全耗尽栅极 - 漏极 电压Vgs = 0伏。

公开(公告)号：US10468526B2

公开(公告)日：2019-11-05

申请号：US15836756

申请日：2017-12-08

申请人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

发明人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/08

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

公开(公告)号：US20160099351A1

公开(公告)日：2016-04-07

申请号：US14507311

申请日：2014-10-06

申请人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

发明人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L29/7828 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66666 ,  H01L29/7806

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件。 半导体功率器件包括沟槽栅极，每个沟槽栅极具有在由侧壁间隔物围绕的半导体衬底的顶表面之上延伸的伸出栅极段。 半导体功率器件还包括与基本上平行于沟槽栅极的侧壁间隔开的开口的槽。 粘贴门区段还包括由侧壁间隔物围绕的绝缘材料构成的盖。 阻挡金属层覆盖盖的顶表面并且覆盖在侧壁间隔物上并在槽的顶表面上方延伸。 这些槽填充有与栅极段相同的栅极材料，用作附加栅电极，用于提供向沟槽栅极延伸的耗尽层，借此栅极与沟槽栅极之间的漂移区域完全耗尽栅极 - 漏极 电压Vgs = 0伏。

公开(公告)号：US09882049B2

公开(公告)日：2018-01-30

申请号：US14507311

申请日：2014-10-06

申请人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

发明人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/739 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/08

CPC分类号： H01L29/7828 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66666 ,  H01L29/7806

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

公开(公告)号：US20160005809A1

公开(公告)日：2016-01-07

申请号：US14298537

申请日：2014-06-06

申请人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/06 ,  H01L21/761

CPC分类号： H01L29/0634 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/6609 ,  H01L29/861

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

公开(公告)号：US09231050B1

公开(公告)日：2016-01-05

申请号：US14298537

申请日：2014-06-06

申请人： Madhur Bobde ,  Lingping Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingping Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L21/761

CPC分类号： H01L29/0634 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/6609 ,  H01L29/861

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

公开(公告)号：US08803251B2

公开(公告)日：2014-08-12

申请号：US13135982

申请日：2011-07-19

申请人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

发明人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。 边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。 边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

公开(公告)号：US08441046B2

公开(公告)日：2013-05-14

申请号：US12925869

申请日：2010-10-31

申请人： Madhur Bobde ,  Anup Bhalla

发明人： Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/66

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/66348

摘要： This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.

摘要翻译： 本发明公开了一种形成在半导体衬底中的绝缘栅双极晶体管（IGBT）器件。 IGBT器件具有分裂屏蔽沟槽栅极，其包括上栅极段和下屏蔽段。 IGBT器件还可以包括填充有离开分屏蔽沟槽栅极一定距离设置的电介质层的虚拟沟槽。 IGBT器件还包括在分屏蔽沟槽栅极和虚拟沟槽之间延伸的体区，其围绕半导体衬底的顶表面附近的分离屏蔽沟槽栅极的源极区域。 所述IGBT器件还包括设置在所述体区域的下方且位于所述半导体衬底的底表面的底体 - 掺杂剂集电极区域上方的源 - 掺杂剂漂移区上方的重掺杂N区域。 在替代实施例中，IGBT可以包括具有沟槽屏蔽电极的平面栅极。

公开(公告)号：US20130001695A1

公开(公告)日：2013-01-03

申请号：US13171037

申请日：2011-06-28

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/0262 ,  H01L21/8222 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0814 ,  H01L27/082

摘要： An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions are formed within the epitaxial layer. A first source region is transversely adjacent the first body region between first and second trigger regions laterally adjacent the first source region and transversely adjacent the first body region. A second source region is located transversely adjacent the second body region between third and fourth trigger regions laterally adjacent the second source region and transversely adjacent the second body region. A third source region is laterally adjacent the fourth trigger region. The fourth trigger region is between the second and third source regions. An implant region within the fourth trigger region is laterally adjacent the third source region.

摘要翻译： 外延层支撑在基板的顶部。 第一和第二体区域形成在外延层中以预定的横向距离分开。 在外延层内形成触发源区和源极区。 第一源区域横向地邻近第一和第二触发区域之间的与第一源区域相邻并且横向邻近第一体区域的第一体区域相邻。 第二源区域横向地邻近第二和第四触发区域之间的第二体区横向邻近第二源区域并且横向邻近第二体区域定位。 第三源区域与第四触发区域横向相邻。 第四触发区域在第二和第三源区之间。 第四触发区域内的植入区域与第三源区域横向相邻。

公开(公告)号：US20170213887A1

公开(公告)日：2017-07-27

申请号：US15479281

申请日：2017-04-05

申请人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

发明人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/739 ,  H01L29/49 ,  H01L29/872

CPC分类号： H01L29/0634 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.