公开(公告)号：US07091558B2

公开(公告)日：2006-08-15

申请号：US10763818

申请日：2004-01-23

申请人： Ferruccio Frisina ,  Giuseppe Ferla ,  Angelo Magri′ ,  Dario Salinas

发明人： Ferruccio Frisina ,  Giuseppe Ferla ,  Angelo Magri′ ,  Dario Salinas

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/66712

摘要： A MOS power device having: a body; gate regions on top of the body and delimiting therebetween a window; a body region, extending in the body underneath the window; a source region, extending inside the body region throughout the width of the window; body contact regions, extending through the source region up to the body region; source contact regions, extending inside the source region, at the sides of the body contact regions; a dielectric region on top of the source region; openings traversing the dielectric region on top of the body and source contact regions; and a metal region extending above the dielectric region and through the first and second openings.

摘要翻译： 一种MOS功率器件，具有：一体; 门体区域，并在其间界定窗口; 身体区域，在窗户下方的身体延伸; 源区域，在整个窗口的宽度内在体区内延伸; 身体接触区域，延伸穿过源区域直到身体区域; 源极接触区域，在源极区域内延伸，位于身体接触区域的侧面; 位于源极区顶部的电介质区域; 穿过主体和源接触区域顶部的电介质区域的开口; 以及在电介质区域上延伸并穿过第一和第二开口的金属区域。

公开(公告)号：US07084034B2

公开(公告)日：2006-08-01

申请号：US10430771

申请日：2003-05-06

申请人： Ferruccio Frisina

发明人： Ferruccio Frisina

IPC分类号： H01L21/336 ,  H01L21/425 ,  H01L21/332

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/66712

摘要： MOS-gated power device including a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type. A plurality of doped regions of a first conductivity type is formed in the semiconductor material layer, each one of the doped regions being disposed under a respective body region and being separated from other doped regions by portions of the semiconductor material layer.

摘要翻译： 包括多个基本功能单元的MOS门控功率器件，每个基本功能单元包括形成在第二导电类型的半导体材料层中的第一导电类型的体区。 在半导体材料层中形成第一导电类型的多个掺杂区域，每个掺杂区域设置在相应的主体区域下方，并且通过半导体材料层的一部分与其它掺杂区域分离。

公开(公告)号：US20050139906A1

公开(公告)日：2005-06-30

申请号：US10749134

申请日：2003-12-30

申请人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

发明人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/94

CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66712

摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

摘要翻译： 具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。 栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。 第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

公开(公告)号：US06369425B1

公开(公告)日：2002-04-09

申请号：US08811363

申请日：1997-03-06

申请人： Giuseppe Ferla ,  Ferruccio Frisina

发明人： Giuseppe Ferla ,  Ferruccio Frisina

IPC分类号： H01L2976

CPC分类号： H01L29/66719 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712 ,  Y10S148/126

摘要： A process for manufacturing high-density MOS-technology power devices includes the steps of: forming a conductive insulated gate layer on a surface of a lightly doped semiconductor material layer of a first conductivity type; forming an insulating material layer over the insulated gate layer; selectively removing the insulating material layer and the underlying insulated gate layer to form a plurality of elongated windows having two elongated edges and two short edges, delimiting respective uncovered surface stripes of the semiconductor material layer; implanting a high dose of a first dopant of the first conductivity type along two directions which lie in a plane transversal to said elongated windows and orthogonal to the semiconductor material layer surface, and which are substantially symmetrically tilted at a first prescribed angle with respect to a direction orthogonal to the semiconductor material layer surface, the first angle depending on the overall thickness of the insulated gate layer and of the insulating material layer to prevent the first dopant from being implanted in a central stripe of said uncovered surface stripes, to form pairs of heavily doped elongated source regions of the first conductivity type which extend along said two elongated edges of each elongated window and which are separated by said central stripe; implanting a low dose of a second dopant of a second conductivity type along two directions which lie in said plane, and which are substantially symmetrically tilted of a second prescribed angle with respect to said orthogonal direction, to form doped regions of the second conductivity type each comprising two lightly doped elongated channel regions extending under the two elongated edges of each elongated window; implanting a high dose of a third dopant of the second conductivity type substantially along said orthogonal direction, the insulating material layer acting as a mask, to form heavily doped regions substantially aligned with the edges of the elongated windows.

公开(公告)号：US06326271B2

公开(公告)日：2001-12-04

申请号：US09746789

申请日：2000-12-21

申请人： Angelo Magri' ,  Raffaele Zambrano ,  Ferruccio Frisina

发明人： Angelo Magri' ,  Raffaele Zambrano ,  Ferruccio Frisina

IPC分类号： H01L21336

CPC分类号： H01L29/7802 ,  H01L29/0611 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66712

摘要： A MOS technology power device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type superimposed over the semiconductor substrate, an insulated gate layer covering the semiconductor layer, a plurality of substantially rectilinear elongated openings parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes of a second conductivity type formed in the semiconductor layer under the elongated openings, source regions of the first conductivity type included in the body stripes and a metal layer covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings. Each body stripe comprises first portions substantially aligned with a first edge of the respective elongated opening and extending under a second edge of the elongated opening to form a channel region, each first portion including a source region extending substantially from a longitudinal axis of symmetry of the respective elongated opening to the second edge of the elongated opening, and second portions, longitudinally intercalated with the first portions, substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from the longitudinal axis of symmetry to the first edge of the elongated opening, the first portions and second portions of the body stripes being respectively aligned in a direction transversal to the longitudinal axis.

公开(公告)号：US06271061B1

公开(公告)日：2001-08-07

申请号：US09354880

申请日：1999-07-16

申请人： Ferruccio Frisina ,  Leonardo Fragapane

发明人： Ferruccio Frisina ,  Leonardo Fragapane

IPC分类号： H01L21332

CPC分类号： H01L29/66333 ,  H01L29/7395

摘要： A semiconductor power device comprising an insulated gate bipolar transistor, of the type which comprises a semiconductor substrate with a first type of conductivity and an overlying epitaxial layer with a second type of conductivity, opposite from the first, and whose junction to the substrate forms the base/emitter junction of the bipolar transistor, has the junction formed by a layer of semiconductor material with conductivity of the second type but a higher concentration of dopant than that of the epitaxial layer. Furthermore, the device has the epitaxial layer with conductivity of the second type provided with at least two zones at different dopant concentrations, namely a first lower zone being part of the junction and having a higher dopant concentration, and a second upper zone having a lower concentration.

摘要翻译： 一种半导体功率器件，包括绝缘栅双极晶体管，其类型包括具有第一导电类型的半导体衬底和具有与第一导电相反的第二导电类型的上覆外延层，并且其与衬底的结到其形成 双极晶体管的基极/发射极结具有由具有第二类型的导电性但具有比外延层更高的掺杂剂浓度的半导体材料层形成的结。 此外，器件具有第二类型的具有导电性的外延层，其具有不同掺杂剂浓度的至少两个区域，即，第一下部区域是结的一部分并且具有较高的掺杂剂浓度，以及具有较低掺杂剂浓度的第二上部区域 浓度。

公开(公告)号：US6090669A

公开(公告)日：2000-07-18

申请号：US731104

申请日：1996-10-09

申请人： Giovanni Franco ,  Cateno Marco Camalleri ,  Ferruccio Frisina

发明人： Giovanni Franco ,  Cateno Marco Camalleri ,  Ferruccio Frisina

IPC分类号： H01L21/761 ,  H01L21/225 ,  H01L21/265 ,  H01L29/06 ,  H01L21/336

CPC分类号： H01L21/2253 ,  H01L29/0615 ,  H01L29/0619

摘要： A fabrication method for high voltage power devices with at least one deep edge ring includes the steps of growing a lightly doped N-type epitaxial layer on a heavily doped N-type substrate, growing an oxide on the upper portion of the epitaxial layer, masking and then implanting boron ions, etching the oxide to expose regions for aluminum ion implantation, forming a layer of preimplantation oxide, masking of the body regions with a layer of photosensitive material and implanting aluminum ions, and a single thermal diffusion process forming a layer of thermal oxide on the epitaxial layer and simultaneously forming at least one deep aluminum ring and an adjacent body region doped with boron.

摘要翻译： 具有至少一个深边缘环的高电压功率器件的制造方法包括以下步骤：在重掺杂的N型衬底上生长轻掺杂的N型外延层，在外延层的上部生长氧化物，掩模 然后注入硼离子，蚀刻氧化物以暴露用于铝离子注入的区域，形成预植入氧化物层，用感光材料层掩蔽身体区域并注入铝离子，以及形成一层 并且同时形成至少一个深铝环和掺杂有硼的相邻体区。

公开(公告)号：US6054737A

公开(公告)日：2000-04-25

申请号：US738584

申请日：1996-10-29

申请人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

发明人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/74

CPC分类号： H01L29/66712 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/0847

摘要： A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window. The second insulating material layer includes a second elongated window extending above each elongated body region. The second insulating material layer seals the edges of the conductive material layer from a source metal layer disposed over the second insulating material layer. The source metal layer contacts each body region and each source region through each second elongated window along the length of the elongated body region.

公开(公告)号：US6051862A

公开(公告)日：2000-04-18

申请号：US184894

申请日：1998-11-03

申请人： Antonio Grimaldi ,  Antonino Schillaci ,  Ferruccio Frisina ,  Giuseppe Ferla

发明人： Antonio Grimaldi ,  Antonino Schillaci ,  Ferruccio Frisina ,  Giuseppe Ferla

IPC分类号： H01L21/336 ,  H01L23/482 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66712 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/7802 ,  H01L29/41725 ,  H01L2924/0002

摘要： A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the second conductivity type extending substantially in parallel to each other and at least one source region of the first conductivity type disposed within each body stripe. A conductive gate layer is insulatively disposed over the semiconductor material layer between the body stripes in the form of a first web structure. A second web structure of the second conductivity type is formed in the semiconductor material layer and comprises an annular frame portion surrounding the plurality of body stripes and at least one first elongated stripe extending between two sides of the annular frame portion in a direction substantially orthogonal to the body stripes and that is merged at each end with the annular frame portion. The body stripes are divided by the at least one first elongated stripe into at least two groups of body stripes, wherein one end of each body stripe is merged with the annular frame portion of the second conductivity type and the other end is merged with the at least one first elongated stripe. A conductive gate finger is insulatively disposed above the first elongated stripe and is part of the first web structure. A conductive gate ring surrounds the conductive gate layer and the conductive gate finger and completes the first web structure. A metal gate finger is disposed above the conductive gate finger and is merged at its ends with a metal gate ring structure disposed above the conductive gate ring to provide a third web structure. Source metal plates cover the at least two groups of body stripes and contact each source region and each body stripe to form a source electrode of the power device. A bottom surface of the semiconductor material layer forms a drain of the power device.

公开(公告)号：US6030870A

公开(公告)日：2000-02-29

申请号：US960561

申请日：1997-10-29

申请人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

发明人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/0847

摘要： A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window. The second insulating material layer includes a second elongated window extending above each elongated body region. The second insulating material layer seals the edges of the conductive material layer from a source metal layer disposed over the second insulating material layer. The source metal layer contacts each body region and each source region through each second elongated window along the length of the elongated body region.