公开(公告)号：US5953613A

公开(公告)日：1999-09-14

申请号：US811415

申请日：1997-03-04

申请人： Mark I. Gardner ,  Frederick N. Hause

发明人： Mark I. Gardner ,  Frederick N. Hause

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/66628 ,  H01L21/76838 ,  H01L21/823468 ,  H01L23/485 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/7835 ,  H01L2924/0002

摘要： The ultimate shallow source drain junction depth for a transistor is achieved by removing or detaching a source from the semiconductor substrate and forming an electron source on the surface of the semiconductor substrate adjacent to the transistor gate. The removal or detachment of an electron source from the semiconductor substrate eliminates the heavily-doped source drain diffusion or implant into a source region of the substrate, thereby avoiding non-uniform doping profiles that degrade long-channel subthreshold characteristics of a device as well as the punchthrough behavior of short-channel devices. A metal plug is used as an electron source which is removed or detached from the from the semiconductor substrate. The metal plug is vastly superior to doped semiconductor materials as an electron source. A method of fabricating an integrated circuit includes forming a lightly-doped drain (LDD) MOSFET structure prior to source/drain doping. The MOSFET structure includes a gate formed on a substrate over a gate oxide layer, spacers formed on sides of the gate, LDD doping of the substrate in a source region and a drain region self-aligned with the gate, and drain doping in the drain region self-aligned with the gate and spacers. The method further includes forming an oxide layer over the substrate and LDD MOSFET structure, forming a polysilicon layer over the oxide layer, cutting a via through the polysilicon layer and source layer to the substrate surface adjacent to the gate and spacer and abutting the source region of the substrate, and forming a metal plug in the via, the metal plug electrically coupling to the LDD doping in the source region of the substrate and electrically coupling to the polysilicon layer, the metal plug serving as a source for the MOSFET.

摘要翻译： 通过从半导体衬底去除或分离源极并在与晶体管栅极相邻的半导体衬底的表面上形成电子源来实现晶体管的最终浅源极漏极结深度。 从半导体衬底去除或分离电子源消除了重掺杂源极漏极扩散或注入到衬底的源极区域中，从而避免了劣化器件的长沟道亚阈值特性的不均匀掺杂分布，以及 短通道设备的突破行为。 使用金属塞作为从半导体基板去除或分离的电子源。 金属插头比作为电子源的掺杂半导体材料显着优越。 制造集成电路的方法包括在源极/漏极掺杂之前形成轻掺杂漏极（LDD）MOSFET结构。 MOSFET结构包括形成在栅极氧化物层上的衬底上的栅极，形成在栅极侧面的间隔物，源极区中的衬底的LDD掺杂和与栅极自对准的漏极区以及漏极中的漏极掺杂 区域与栅极和间隔物自对准。 该方法还包括在衬底和LDD MOSFET结构之上形成氧化物层，在氧化物层上形成多晶硅层，将通过多晶硅层和源极层的通孔切割到与栅极和间隔物相邻的衬底表面，并邻接源区 并且在所述通孔中形成金属插塞，所述金属插塞电耦合到所述衬底的所述源极区域中的LDD掺杂并电耦合到所述多晶硅层，所述金属插塞用作所述MOSFET的源极。

公开(公告)号：US5943596A

公开(公告)日：1999-08-24

申请号：US927097

申请日：1997-08-29

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/3205

CPC分类号： H01L21/28194 ,  H01L21/28097 ,  H01L21/28114 ,  H01L29/517 ,  H01L29/66583 ,  H01L29/78391 ,  H01L29/4975

摘要： A semiconductor device having a gate electrode stack formed using a patterned oxide layer is disclosed. The device is formed by forming an oxide layer over a surface of a substrate and forming at least one opening in the oxide layer. A high permittivity plug (e.g., a BST plug) is formed in the lower portion of the opening. A conductive plug (e.g., a metal silicide plug) is formed in an upper portion of the opening over the high permittivity plug. Remaining portions of the oxide layer are then removed. The conductive plug and high permittivity plug may form a gate electrode and a gate insulating layer, respectively.

摘要翻译： 公开了一种具有使用图案化氧化物层形成的栅电极堆叠的半导体器件。 该器件通过在衬底的表面上形成氧化物层并在氧化物层中形成至少一个开口而形成。 在开口的下部形成有高介电常数的插塞（例如，BST插头）。 导电插头（例如，金属硅化物插塞）形成在高介电常数插头上的开口的上部。 然后除去氧化物层的剩余部分。 导电插塞和高电容率插头可分别形成栅电极和栅极绝缘层。

公开(公告)号：US5918133A

公开(公告)日：1999-06-29

申请号：US993029

申请日：1997-12-18

申请人： Mark I. Gardner ,  Robert Paiz

发明人： Mark I. Gardner ,  Robert Paiz

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/32 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L21/31 ,  H01L21/3115

CPC分类号： H01L21/28202 ,  H01L21/26506 ,  H01L21/2822 ,  H01L21/32 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66659 ,  H01L21/28194

摘要： Generally, the present invention relates to a semiconductor device having a dual thickness gate dielectric along the channel and a process of fabricating such a device. By providing a dual thickness gate dielectric, the gate dielectric can, for example, be optimized to the transistor and device performance can be enhanced.

摘要翻译： 通常，本发明涉及一种具有沿通道的双重厚度栅极电介质的半导体器件和制造这种器件的工艺。 通过提供双厚度栅极电介质，栅极电介质例如可以优化到晶体管，并且可以提高器件性能。

公开(公告)号：US5918130A

公开(公告)日：1999-06-29

申请号：US929197

申请日：1997-09-08

申请人： Fred N. Hause ,  Mark I. Gardner ,  H. Jim Fulford, Jr.

发明人： Fred N. Hause ,  Mark I. Gardner ,  H. Jim Fulford, Jr.

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66621 ,  H01L29/7834 ,  Y10S148/10 ,  Y10S438/951

摘要： The present invention advantageously provides a method for forming a transistor in which silicide contact areas are formed to the junctions during fabrication of the transistor. The silicide contact areas may be formed using a single high temperature anneal since silicide forming near sidewalls of the gate oxide is prevented. In one embodiment, dopants are first forwarded into a lateral region of a silicon-based substrate to form an implant region. Then a silicide layer is formed across the implant region using a high temperature anneal. A sacrificial material is deposited across the silicide layer and the substrate. A contiguous opening is formed vertically through the sacrificial material and the silicide layer, exposing a portion of the substrate. Dopants of the type opposite to the dopants implanted previously are then implanted into the exposed substrate region to form a channel. Thus, the implant region is separated into source and drain regions having a channel interposed between them. Spacers may be formed on opposed sidewall surfaces of the sacrificial material within the opening. A gate oxide is then formed across the exposed region, followed by the formation of a polysilicon gate conductor across the gate oxide. A polycide is formed across the gate conductor before the sacrificial material is removed.

摘要翻译： 本发明有利地提供了一种形成晶体管的方法，其中在晶体管的制造期间，其中形成硅化物接触区域到结。 可以使用单个高温退火来形成硅化物接触区域，因为防止在栅极氧化物的侧壁附近形成硅化物。 在一个实施例中，首先将掺杂剂转移到硅基衬底的横向区域中以形成植入区域。 然后使用高温退火在所述注入区域上形成硅化物层。 在硅化物层和衬底之间沉积牺牲材料。 通过牺牲材料和硅化物层垂直地形成连续的开口，暴露基板的一部分。 然后将与先前注入的掺杂剂相反的类型的掺杂剂注入暴露的衬底区域中以形成沟道。 因此，注入区被分离成具有介于它们之间的通道的源区和漏区。 间隔件可以形成在开口内的牺牲材料的相对的侧壁表面上。 然后在暴露区域之间形成栅极氧化物，随后在栅极氧化物上形成多晶硅栅极导体。 在除去牺牲材料之前，跨越栅极导体形成多晶硅化物。

公开(公告)号：US5918128A

公开(公告)日：1999-06-29

申请号：US93423

申请日：1998-06-08

申请人： Mark I. Gardner ,  John J. Bush

发明人： Mark I. Gardner ,  John J. Bush

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/28123 ,  H01L29/7835

摘要： An integrated circuit fabrication process is provided in which a transistor having an ultra short channel length is formed by multiple etchings of a gate conductor layer. After formation of the gate conductor using a photolithographic process, the lateral length of the gate conductor is reduced by forming a masking layer upon the gate conductor such that only a portion of the gate conductor is covered by the masking layer. The unmasked portion of the gate conductor is then removed to reduce the lateral length of the gate conductor. In this manner, a gate conductor having a lateral length that is significantly less than a lateral length attainable using a photolithographic process may be obtained.

摘要翻译： 提供了一种集成电路制造工艺，其中通过栅极导体层的多次蚀刻形成具有超短沟道长度的晶体管。 在使用光刻工艺形成栅极导体之后，通过在栅极导体上形成掩模层来减小栅极导体的横向长度，使得只有栅极导体的一部分被掩蔽层覆盖。 然后去除栅极导体的未屏蔽部分以减小栅极导体的横向长度。 以这种方式，可以获得具有显着小于使用光刻工艺可获得的横向长度的横向长度的栅极导体。

公开(公告)号：US5916715A

公开(公告)日：1999-06-29

申请号：US925382

申请日：1997-09-08

申请人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Fred N. Hause

发明人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Fred N. Hause

IPC分类号： G01R31/28 ,  G03F7/20 ,  G03F9/00

CPC分类号： G03F7/70633 ,  G01R31/2805 ,  G03F7/70658 ,  G01R31/2813

摘要： The present invention advantageously provides a method for determining lithographic misalignment of a via relative to an electrically active area. An electrically measured test structure is provided which is designed to have targeted via areas shifted from the midline(s) of a targeted active area(s). Further, the test structure is designed to have a test pad(s) that electrically communicates with the targeted active area(s). Design specifications of the test structure require the targeted via areas to be offset from the midline(s) of the active area(s) by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to conductors coupled to each of the vias while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a via is misaligned from its desired location. Using the electrical responses for all the vias, it is possible to determine the direction and amount of misalignment.

摘要翻译： 本发明有利地提供了一种用于确定通孔相对于电活动区域的光刻未对准的方法。 提供电测量的测试结构，其被设计成具有从目标有源区域的中线偏移的目标通孔区域。 此外，测试结构被设计成具有与目标有源区域电连通的测试焊盘。 测试结构的设计规范要求目标通孔区域通过变化的距离偏离有效区域的中线。 上述方法涉及处理设计的测试结构。 然后可以将电信号施加到耦合到每个通孔的导体，同时它也被施加到测试垫。 所产生的电响应应与通孔与其所需位置不对准的距离成正比。 使用所有通孔的电响应，可以确定未对准的方向和量。

公开(公告)号：US5905285A

公开(公告)日：1999-05-18

申请号：US31570

申请日：1998-02-26

申请人： Mark I. Gardner ,  Fred N. Hause

发明人： Mark I. Gardner ,  Fred N. Hause

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L29/66621 ,  H01L29/7834 ,  Y10S257/90

摘要： A field effect transistor comprising a semiconductor substrate having a transistor trench extending downward from an upper surface of the semiconductor substrate. The trench extends to a trench depth below an upper surface of the semiconductor substrate. The transistor further includes a gate dielectric layer that is formed on a floor of the transistor trench over a channel region of the semiconductor substrate. A conductive gate structure is formed above and in contact with the gate dielectric layer. A source/drain impurity distribution is formed within a source/drain region of the semiconductor substrate. The source/drain region is laterally disposed on either side of the channel region of the semiconductor substrate. In a preferred embodiment, the trench depth is between 1,000-5,000 angstroms and a thickness of the conductive gate structure is less than 5,000 angstroms such that an upper surface of the conductive gate structure is level with or below an upper surface of the semiconductor substrate. The gate dielectric layer suitably comprises a thermal oxide having a thickness of approximately 20-200 angstroms. In a lightly doped drain (LDD) embodiment, the source/drain impurity distribution includes a lightly doped region and a heavily doped region. The lightly doped region extends laterally from the channel region of the transistor to the heavily doped region. In the preferred embodiment, a lateral dimension of the channel region of the transistor is approximately 100-300 nm.

摘要翻译： 一种场效应晶体管，包括具有从半导体衬底的上表面向下延伸的晶体管沟槽的半导体衬底。 沟槽延伸到半导体衬底的上表面下方的沟槽深度。 晶体管还包括形成在半导体衬底的沟道区上的晶体管沟槽的底板上的栅介质层。 导电栅极结构形成在栅介电层的上方并与其接触。 源极/漏极杂质分布形成在半导体衬底的源极/漏极区域内。 源极/漏极区域横向地设置在半导体衬底的沟道区域的任一侧上。 在优选实施例中，沟槽深度在1,000-5,000埃之间，并且导电栅极结构的厚度小于5000埃，使得导电栅极结构的上表面与半导体衬底的上表面平行或低于半导体衬底的上表面。 栅介质层适当地包括厚度约为20-200埃的热氧化物。 在轻掺杂漏极（LDD）实施例中，源极/漏极杂质分布包括轻掺杂区域和重掺杂区域。 轻掺杂区域从晶体管的沟道区域横向延伸到重掺杂区域。 在优选实施例中，晶体管的沟道区的横向尺寸约为100-300nm。

公开(公告)号：US5885887A

公开(公告)日：1999-03-23

申请号：US847752

申请日：1997-04-21

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/38

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L21/823842 ,  H01L29/42376

摘要： A method of making an IGFET with a selectively doped multilevel polysilicon gate that includes upper and lower polysilicon gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a a lower polysilicon layer on the gate insulator, forming a first masking layer over the lower polysilicon layer, etching the lower polysilicon layer through openings in the first masking layer using the first masking layer as an etch mask for a portion of the lower polysilicon layer that forms the lower polysilicon gate level over the active region, removing the first masking layer, forming the upper polysilicon gate level on the lower polysilicon gate level after removing the first masking layer, introducing a dopant into the upper polysilicon gate level without introducing the dopant into the substrate, diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level, and forming a source and drain in the active region. Advantageously, the lower polysilicon gate level has both an accurately defined length to provide the desired channel length and a well-controlled doping concentration to provide the desired threshold voltage.

摘要翻译： 公开了一种制造具有选择性掺杂多电平多晶硅栅极的IGFET的方法，其包括上和下多晶硅栅极电平。 该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上形成下部多晶硅层，在下部多晶硅层上形成第一掩蔽层，通过下部多晶硅层的开口蚀刻下部多晶硅层 所述第一掩模层使用所述第一掩模层作为用于在所述有源区上形成所述下多晶硅栅极电平的所述下多晶硅层的一部分的蚀刻掩模，去除所述第一掩模层，在所述下多晶硅栅极上形成所述上多晶硅栅极电平 在去除第一掩模层之后，将掺杂剂引入上多晶硅栅极级，而不将掺杂剂引入衬底中，将掺杂剂从上多晶硅栅极级扩散到下多晶硅栅极电平，并在活性层中形成源极和漏极 地区。 有利地，下多晶硅栅极电平具有精确限定的长度以提供期望的沟道长度和良好控制的掺杂浓度以提供期望的阈值电压。

公开(公告)号：US5882973A

公开(公告)日：1999-03-16

申请号：US789549

申请日：1997-01-27

申请人： Mark I. Gardner ,  Fred N. Hause ,  H. Jim. Fulford, Jr.

发明人： Mark I. Gardner ,  Fred N. Hause ,  H. Jim. Fulford, Jr.

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823468 ,  H01L21/823864

摘要： An integrated circuit is provided having a plurality of transistors either NMOS transistors, or PMOS transistors, or both NMOS and PMOS transistors. The transistors are formed having dissimilarly sized spacers. The spacers can be made larger in lateral areas on transistors designated as lower performing transistors than smaller spacers used on transistors which are higher performing. The dissimilarly sized spacers produce correspondingly sized lightly doped drain (LDD) areas. Accordingly, the present integrated circuit includes on a single monolithic substrate both high and low performance transistors based upon formation of dissimilarly sized spacers at sidewall surfaces of select transistor gate conductors.

摘要翻译： 提供了具有多个晶体管的集成电路，NMOS晶体管或PMOS晶体管，或NMOS晶体管和PMOS晶体管。 晶体管形成为具有不同尺寸的间隔物。 在表现较高的晶体管上使用的间隔物可以比被称为低性能晶体管的晶体管的横向区域更大。 不同尺寸的间隔件产生相应尺寸的轻掺杂漏极（LDD）区域。 因此，本集成电路基于在选择晶体管栅极导体的侧壁表面处形成不同尺寸的间隔物，在单个单片基板上包括高性能和低性能晶体管。

公开(公告)号：US5882959A

公开(公告)日：1999-03-16

申请号：US729810

申请日：1996-10-08

申请人： Daniel Kadosh ,  Mark I. Gardner

发明人： Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L21/00

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  Y10S257/905

摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity and capacitance by forming a single gate conductor which is shared by an upper level transistor and a lower level transistor. The shared gate conductor is interposed between a pair of gate dielectrics and each gate dielectric is configured between the single gate conductor and a respective substrate. Thus, the upper level transistor is inverted relative to the lower level transistor. The upper level transistor includes a substrate and junction region formed within and opening of an interlevel dielectric. The opening serves to receive the substrate material, but also to demarcate the formation of a pre-existing gate dielectric prior to substrate deposition. Sharing a single gate conductor among two transistors not only minimizes the overall routing between transistor inputs, but also is particularly attuned to inverter formation.